Lines Matching refs:ShiftReg
884 unsigned ShiftReg; member
1399 RegShiftedReg.ShiftReg); in isRegShiftedReg()
2560 Inst.addOperand(MCOperand::createReg(RegShiftedReg.ShiftReg)); in addRegShiftedRegOperands()
3649 unsigned ShiftReg, unsigned ShiftImm, SMLoc S, in CreateShiftedRegister() argument
3654 Op->RegShiftedReg.ShiftReg = ShiftReg; in CreateShiftedRegister()
3997 << RegName(RegShiftedReg.ShiftReg) << ">"; in print()
4175 int ShiftReg = 0; in tryParseShiftRegister() local
4180 ShiftReg = SrcReg; in tryParseShiftRegister()
4215 ShiftReg = tryParseRegister(); in tryParseShiftRegister()
4216 if (ShiftReg == -1) { in tryParseShiftRegister()
4227 if (ShiftReg && ShiftTy != ARM_AM::rrx) in tryParseShiftRegister()
4229 ShiftReg, Imm, in tryParseShiftRegister()