| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | IntrinsicLowering.cpp | 193 Value *ShVal = ConstantInt::get(V->getType(), i); in LowerCTLZ() local
194 ShVal = Builder.CreateLShr(V, ShVal, "ctlz.sh"); in LowerCTLZ()
195 V = Builder.CreateOr(V, ShVal, "ctlz.step"); in LowerCTLZ()
|
| /llvm-project-15.0.7/llvm/lib/Transforms/Utils/ |
| H A D | VNCoercion.cpp | 541 Value *ShVal = Builder.CreateShl( in getMemInstValueForLoad() local
543 Val = Builder.CreateOr(Val, ShVal); in getMemInstValueForLoad()
549 Value *ShVal = in getMemInstValueForLoad() local
551 Val = Builder.CreateOr(OneElt, ShVal); in getMemInstValueForLoad()
|
| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonLoopIdiomRecognition.cpp | 1439 Value *ShAmt = CIV, *ShVal = Op; in convertShiftsToLeft() local
1440 auto *VTy = cast<IntegerType>(ShVal->getType()); in convertShiftsToLeft()
1443 ShVal = IRB.CreateShl(Op, ConstantInt::get(VTy, 1)); in convertShiftsToLeft()
1448 ShVal = upcast(CastMap, IRB, ShVal, ATy); in convertShiftsToLeft()
1453 W = IRB.CreateShl(ShVal, ShAmt); in convertShiftsToLeft()
|
| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 2262 SDValue ShVal = N.getOperand(0); in matchAddressRecursively() local
2267 if (CurDAG->isBaseWithConstantOffset(ShVal)) { in matchAddressRecursively()
2268 AM.IndexReg = ShVal.getOperand(0); in matchAddressRecursively()
2269 ConstantSDNode *AddVal = cast<ConstantSDNode>(ShVal.getOperand(1)); in matchAddressRecursively()
2275 AM.IndexReg = ShVal; in matchAddressRecursively()
|
| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 2388 uint64_t ShVal = ShAmtC->getZExtValue(); in SimplifyDemandedBits() local
2392 HighBits.lshrInPlace(ShVal); in SimplifyDemandedBits()
2399 ShVal, dl, getShiftAmountTy(VT, DL, TLO.LegalTypes())); in SimplifyDemandedBits()
2488 unsigned ShVal = Op.getValueSizeInBits() - 1; in SimplifyDemandedBits() local
2489 SDValue ShAmt = TLO.DAG.getConstant(ShVal, dl, VT); in SimplifyDemandedBits()
7250 SDValue ShVal; in expandROT() local
7257 ShVal = DAG.getNode(ShOpc, DL, VT, Op0, ShAmt); in expandROT()
7265 ShVal = DAG.getNode(ShOpc, DL, VT, Op0, ShAmt); in expandROT()
7271 return DAG.getNode(ISD::OR, DL, VT, ShVal, HsVal); in expandROT()
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 497 unsigned ShVal = AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt); in SelectArithImmed() local
500 Shift = CurDAG->getTargetConstant(ShVal, dl, MVT::i32); in SelectArithImmed()
618 unsigned ShVal = AArch64_AM::getShifterImm(ShType, Val); in SelectShiftedRegister() local
621 Shift = CurDAG->getTargetConstant(ShVal, SDLoc(N), MVT::i32); in SelectShiftedRegister()
|
| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 5898 Register ShVal; in lowerRotate() local
5905 ShVal = MIRBuilder.buildInstr(ShOpc, {DstTy}, {Src, ShAmt}).getReg(0); in lowerRotate()
5914 ShVal = MIRBuilder.buildInstr(ShOpc, {DstTy}, {Src, ShAmt}).getReg(0); in lowerRotate()
5921 MIRBuilder.buildOr(Dst, ShVal, RevShiftVal); in lowerRotate()
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 5946 unsigned ShVal = AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt); in select12BitValueWithLeftShift() local
5949 [=](MachineInstrBuilder &MIB) { MIB.addImm(ShVal); }, in select12BitValueWithLeftShift()
|