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Searched refs:SetCC (Results 1 – 25 of 25) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsetcc-takes-i32.ll4 ; correctly. Previously LLVM thought that i64 was the appropriate SetCC output,
8 ; It was expecting the smallest legal promotion of i1 to be the preferred SetCC
/llvm-project-15.0.7/llvm/test/Transforms/InstSimplify/ConstProp/
H A D2002-09-03-SetCC-Bools.ll1 ; SetCC on boolean values was not implemented!
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp1264 SDValue SetCC = DAG.getSetCC(dl, MVT::i32, ShAmt, Zero, ISD::SETEQ); in LowerSHL_PARTS() local
1265 LoBitsForHi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, LoBitsForHi); in LowerSHL_PARTS()
1275 SetCC = DAG.getSetCC(dl, MVT::i32, ExtraShAmt, Zero, ISD::SETGE); in LowerSHL_PARTS()
1277 DAG.getSelect(dl, MVT::i32, SetCC, HiForBigShift, HiForNormalShift); in LowerSHL_PARTS()
1283 dl, MVT::i32, SetCC, DAG.getConstant(0, dl, MVT::i32), LoForNormalShift); in LowerSHL_PARTS()
1312 SDValue SetCC = DAG.getSetCC(dl, MVT::i32, NegatedPlus32, Zero, ISD::SETLE); in LowerSRL_PARTS() local
1315 Hi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, Hi); in LowerSRL_PARTS()
1318 Lo = DAG.getSelect(dl, MVT::i32, SetCC, Hi, Lo); in LowerSRL_PARTS()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrCMovSetCC.td1 //===-- X86InstrCMovSetCC.td - Conditional Move and SetCC --*- tablegen -*-===//
75 // SetCC instructions.
H A DX86ISelLowering.cpp26936 SDValue SetCC; in LowerINTRINSIC_WO_CHAIN() local
26941 SetCC = DAG.getNode(ISD::AND, dl, MVT::i8, SetCC, SetNP); in LowerINTRINSIC_WO_CHAIN()
26947 SetCC = DAG.getNode(ISD::OR, dl, MVT::i8, SetCC, SetP); in LowerINTRINSIC_WO_CHAIN()
31824 SetCC = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC); in LowerADDSUBCARRY()
45185 SDValue SetCC; in checkBoolTestSetCCCombine() local
45191 SetCC = Op2; in checkBoolTestSetCCCombine()
45193 SetCC = Op1; in checkBoolTestSetCCCombine()
45217 SetCC = SetCC.getOperand(OpIdx); in checkBoolTestSetCCCombine()
45220 SetCC = SetCC.getOperand(0); in checkBoolTestSetCCCombine()
50923 return SetCC; in combineXor()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCInstrP10.td1860 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)),
1862 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)),
1864 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)),
1866 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETLE)),
1868 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)),
1886 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)),
1888 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)),
1890 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)),
1892 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETLE)),
1896 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)),
[all …]
H A DPPCInstrInfo.td3705 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)),
3709 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETLE)),
3713 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)),
3715 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETO)),
3718 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETOLT)),
3720 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETLT)),
3722 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETOGT)),
3724 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETGT)),
3726 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETOEQ)),
3728 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETEQ)),
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp662 SDValue SetCC = N->getOperand(0); in performSELECTCombine() local
664 if ((SetCC.getOpcode() != ISD::SETCC) || in performSELECTCombine()
665 !SetCC.getOperand(0).getValueType().isInteger()) in performSELECTCombine()
689 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); in performSELECTCombine()
692 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), in performSELECTCombine()
693 SetCC.getOperand(1), in performSELECTCombine()
696 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True); in performSELECTCombine()
719 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False); in performSELECTCombine()
727 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), in performSELECTCombine()
728 SetCC.getOperand(1), in performSELECTCombine()
[all …]
H A DMipsSEISelLowering.cpp978 SDValue SetCC = N->getOperand(0); in performVSELECTCombine() local
980 if (SetCC.getOpcode() != MipsISD::SETCC_DSP) in performVSELECTCombine()
984 SetCC.getOperand(0), SetCC.getOperand(1), in performVSELECTCombine()
985 N->getOperand(1), N->getOperand(2), SetCC.getOperand(2)); in performVSELECTCombine()
H A DMipsInstrInfo.td1519 // SetCC
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVVPInstrInfo.td104 // SetCC (lhs, rhs, cc, mask, vl)
/llvm-project-15.0.7/llvm/test/CodeGen/Generic/
H A Dselect.ll22 ; A SetCC whose result is used should produce instructions to
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp1414 SDValue SetCC = DAG.getNode(M68kISD::SETCC, DL, N->getValueType(1), in LowerXALUO() local
1418 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Arith, SetCC); in LowerXALUO()
1949 SDValue SetCC = in LowerSETCC() local
1953 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC); in LowerSETCC()
1954 return SetCC; in LowerSETCC()
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dopt-pipeline.ll115 ; CHECK-NEXT: X86 Fixup SetCC
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp16765 const SDValue SetCC = N->getOperand(0); in performSignExtendSetCCCombine() local
16767 const SDValue CCOp0 = SetCC.getOperand(0); in performSignExtendSetCCCombine()
16768 const SDValue CCOp1 = SetCC.getOperand(1); in performSignExtendSetCCCombine()
16779 if (isCheapToExtend(SetCC.getOperand(0)) && in performSignExtendSetCCCombine()
18637 SDValue SetCC = N->getOperand(0); in trySwapVSelectOperands() local
18638 if (SetCC.getOpcode() != ISD::SETCC || !SetCC.hasOneUse()) in trySwapVSelectOperands()
18656 DAG.getSetCC(SDLoc(SetCC), SetCC.getValueType(), SetCC.getOperand(0), in trySwapVSelectOperands()
18684 SDValue SetCC = N->getOperand(0); in performVSelectCombine() local
18685 if (SetCC.getOpcode() == ISD::SETCC && in performVSelectCombine()
18687 SDValue CmpLHS = SetCC.getOperand(0); in performVSelectCombine()
[all …]
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp744 SDValue SetCC = in Expand() local
747 Results.push_back(DAG.getSelect(SDLoc(Node), Node->getValueType(0), SetCC, in Expand()
H A DDAGCombiner.cpp2344 SDValue SetCC = Z.getOperand(0); in foldAddSubBoolOfMaskedVal() local
8477 SDValue SetCC = in visitXOR() local
8480 CombineTo(N, SetCC); in visitXOR()
11469 for (SDNode *SetCC : SetCCs) { in ExtendSetCCUses()
11480 Ops.push_back(SetCC->getOperand(2)); in ExtendSetCCUses()
11481 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0), Ops)); in ExtendSetCCUses()
11685 SDValue SetCC = VSel.getOperand(0); in matchVSelectOpSizesWithSetCC() local
11815 SDValue SetCC = N->getOperand(0); in foldExtendedSignBitTest() local
11817 !SetCC.hasOneUse() || SetCC.getValueType() != MVT::i1) in foldExtendedSignBitTest()
11820 SDValue X = SetCC.getOperand(0); in foldExtendedSignBitTest()
[all …]
H A DLegalizeIntegerTypes.cpp1171 SDValue SetCC; in PromoteIntRes_SETCC() local
1176 SetCC = DAG.getNode(N->getOpcode(), dl, VTs, Opers); in PromoteIntRes_SETCC()
1179 ReplaceValueWith(SDValue(N, 1), SetCC.getValue(1)); in PromoteIntRes_SETCC()
1181 SetCC = DAG.getNode(N->getOpcode(), dl, SVT, N->getOperand(0), in PromoteIntRes_SETCC()
1185 return DAG.getSExtOrTrunc(SetCC, dl, NVT); in PromoteIntRes_SETCC()
H A DTargetLowering.cpp9235 SDValue SetCC; in expandUADDSUBO() local
9242 SetCC = in expandUADDSUBO()
9247 SetCC = DAG.getSetCC(dl, SetCCType, Result, LHS, CC); in expandUADDSUBO()
9249 Overflow = DAG.getBoolExtOrTrunc(SetCC, dl, ResultType, ResultType); in expandUADDSUBO()
9270 SDValue SetCC = DAG.getSetCC(dl, OType, Result, Sat, ISD::SETNE); in expandSADDSUBO() local
9271 Overflow = DAG.getBoolExtOrTrunc(SetCC, dl, ResultType, ResultType); in expandSADDSUBO()
H A DSelectionDAGBuilder.cpp7205 SDValue SetCC = DAG.getSetCC(sdl, CCVT, VectorInduction, in visitIntrinsicCall() local
7207 setValue(&I, SetCC); in visitIntrinsicCall()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp4897 SDValue SetCC = DAG.getNode(AMDGPUISD::SETCC, DL, CCVT, LHS, RHS, in lowerICMPIntrinsic() local
4900 return SetCC; in lowerICMPIntrinsic()
4901 return DAG.getZExtOrTrunc(SetCC, DL, VT); in lowerICMPIntrinsic()
4927 SDValue SetCC = DAG.getNode(AMDGPUISD::SETCC, SL, CCVT, Src0, in lowerFCMPIntrinsic() local
4930 return SetCC; in lowerFCMPIntrinsic()
4931 return DAG.getZExtOrTrunc(SetCC, SL, VT); in lowerFCMPIntrinsic()
5170 SDNode *SetCC = nullptr; in LowerBRCOND() local
5174 SetCC = Intr; in LowerBRCOND()
5175 Intr = SetCC->getOperand(0).getNode(); in LowerBRCOND()
5193 assert(!SetCC || in LowerBRCOND()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp3986 SDValue SetCC = emitSETCC(DAG, DL, Result.getValue(1), CCValid, CCMask); in lowerXALUO() local
3988 SetCC = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC); in lowerXALUO()
3990 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, SetCC); in lowerXALUO()
4052 SDValue SetCC = emitSETCC(DAG, DL, Result.getValue(1), CCValid, CCMask); in lowerADDSUBCARRY() local
4054 SetCC = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC); in lowerADDSUBCARRY()
4056 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, SetCC); in lowerADDSUBCARRY()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp2296 SDValue SetCC = DAG.getNode(ISD::SETCC, dl, ResTy, in WidenHvxSetCC() local
2301 {SetCC, getZero(dl, MVT::i32, DAG)}); in WidenHvxSetCC()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp5206 SDValue SetCC = DAG.getSetCC(DL, XLenVT, Vec, Zero, CC); in lowerVectorMaskVecReduction() local
5209 return SetCC; in lowerVectorMaskVecReduction()
5217 return DAG.getNode(BaseOpc, DL, XLenVT, SetCC, Op.getOperand(0)); in lowerVectorMaskVecReduction()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp12975 SDValue SetCC; in PerformSELECTCombine() local
12984 SetCC = N->getOperand(0); in PerformSELECTCombine()
12985 LHS = SetCC->getOperand(0); in PerformSELECTCombine()
12986 RHS = SetCC->getOperand(1); in PerformSELECTCombine()
12987 CC = cast<CondCodeSDNode>(SetCC->getOperand(2))->get(); in PerformSELECTCombine()