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Searched refs:Scaled (Results 1 – 20 of 20) sorted by relevance

/llvm-project-15.0.7/llvm/tools/llvm-xray/
H A Dxray-color-helper.cpp85 double Scaled[3] = {std::get<0>(Color) / 255.0, std::get<1>(Color) / 255.0, in convertToHSV() local
90 if (Scaled[i] < Scaled[Min]) in convertToHSV()
92 if (Scaled[i] > Scaled[Max]) in convertToHSV()
96 double C = Scaled[Max] - Scaled[Min]; in convertToHSV()
99 (C == 0) ? 0 : (Scaled[(Max + 1) % 3] - Scaled[(Max + 2) % 3]) / C; in convertToHSV()
104 double V = Scaled[Max]; in convertToHSV()
/llvm-project-15.0.7/llvm/include/llvm/Transforms/
H A DInstrumentation.h172 uint64_t Scaled = Count / Scale; in scaleBranchCount() local
173 assert(Scaled <= std::numeric_limits<uint32_t>::max() && "overflow 32-bits"); in scaleBranchCount()
174 return Scaled; in scaleBranchCount()
/llvm-project-15.0.7/llvm/lib/Analysis/
H A DBlockFrequencyInfoImpl.cpp508 Scaled64 Scaled = BFI.Freqs[Index].Scaled * ScalingFactor; in convertFloatingToInteger() local
509 BFI.Freqs[Index].Integer = std::max(UINT64_C(1), Scaled.toInt<uint64_t>()); in convertFloatingToInteger()
511 << BFI.Freqs[Index].Scaled << ", scaled = " << Scaled in convertFloatingToInteger()
534 : BFI.Freqs[N.Index].Scaled; in unwrapLoop()
545 Freqs[Index].Scaled = Working[Index].Mass.toScaled(); in unwrapLoops()
558 Min = std::min(Min, Freqs[Index].Scaled); in finalizeMetrics()
559 Max = std::max(Max, Freqs[Index].Scaled); in finalizeMetrics()
625 return Freqs[Node.Index].Scaled; in getFloatingBlockFreq()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMScheduleV6.td108 // Scaled register offset, issues over 2 cycles
121 // Scaled register offset with update, issues over 2 cycles
161 // Scaled register offset, issues over 2 cycles
174 // Scaled register offset with update, issues over 2 cycles
H A DARMScheduleA8.td123 // Scaled register offset, issues over 2 cycles
144 // Scaled register offset with update, issues over 2 cycles
202 // Scaled register offset, issues over 2 cycles
222 // Scaled register offset with update, issues over 2 cycles
H A DARMScheduleA9.td226 // Scaled register offset
267 // Scaled register offset with update
366 // Scaled register offset
403 // Scaled register offset with update
H A DARMInstrThumb.td89 // Scaled 4 immediate.
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DMachineTraceMetrics.h415 unsigned getCycles(unsigned Scaled) { in getCycles() argument
417 return (Scaled + Factor - 1) / Factor; in getCycles()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DSpillPlacement.cpp254 uint64_t Scaled = (Freq >> 13) + bool(Freq & (1 << 12)); in setThreshold() local
255 Threshold = std::max(UINT64_C(1), Scaled); in setThreshold()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp783 auto Scaled = MGather->isIndexScaled() ? "scaled" : "unscaled"; in print_details() local
784 OS << ", " << Signed << " " << Scaled << " offset"; in print_details()
795 auto Scaled = MScatter->isIndexScaled() ? "scaled" : "unscaled"; in print_details() local
796 OS << ", " << Signed << " " << Scaled << " offset"; in print_details()
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dfast-isel-addressing-modes.ll430 ; Load Scaled Register Offset
455 ; Load Base Register + Scaled Register Offset
637 ; Load Base Register + Scaled Register Offset + Sign/Zero extension
733 ; Load Scaled Register Offset + Immediate Offset + Sign/Zero extension
749 ; Load Base Register + Scaled Register Offset + Immediate Offset + Sign/Zero extension
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dshufflevec-bitcast-inseltpoison.ll69 ; Scaled mask is inverse of first mask.
128 ; Scaled mask is inverse of first mask.
H A Dshufflevec-bitcast.ll69 ; Scaled mask is inverse of first mask.
128 ; Scaled mask is inverse of first mask.
/llvm-project-15.0.7/clang/lib/CodeGen/
H A DCodeGenPGO.cpp1070 uint64_t Scaled = Weight / Scale + 1; in scaleBranchWeight() local
1071 assert(Scaled <= UINT32_MAX && "overflow 32-bits"); in scaleBranchWeight()
1072 return Scaled; in scaleBranchWeight()
/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCInstrInfo.cpp35 Scaled = 3 enumerator
/llvm-project-15.0.7/llvm/include/llvm/Analysis/
H A DBlockFrequencyInfoImpl.h215 Scaled64 Scaled; member
1420 Freqs[Node.Index].Scaled = Freq[BlockIndex[&BB]];
1422 Freqs[Node.Index].Scaled = Scaled64::getZero();
/llvm-project-15.0.7/llvm/lib/Transforms/Utils/
H A DScalarEvolutionExpander.cpp509 Value *Scaled = in expandAddToGEP() local
513 GepIndices.push_back(Scaled); in expandAddToGEP()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64InstrFormats.td4663 // Scaled half-precision to 32-bit
4673 // Scaled half-precision to 64-bit
4682 // Scaled single-precision to 32-bit
4691 // Scaled single-precision to 64-bit
4699 // Scaled double-precision to 32-bit
4708 // Scaled double-precision to 64-bit
4791 // Scaled
H A DAArch64InstrInfo.td3887 // Scaled floating point to integer conversion instructions.
4028 // Scaled integer to floating point conversion instructions.
H A DAArch64ISelLowering.cpp17333 const bool Scaled = Opc == AArch64ISD::GLD1_SCALED_MERGE_ZERO || in performGLD1Combine() local
17369 unsigned NewOpc = getGatherVecOpcode(Scaled, OffsetIsSExt, true); in performGLD1Combine()