Searched refs:STRICT_FSQRT (Results 1 – 12 of 12) sorted by relevance
| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 411 STRICT_FSQRT, enumerator
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| /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
| H A D | irtranslator-constrained-fp.ll | 211 ; CHECK-NEXT: [[STRICT_FSQRT:%[0-9]+]]:_(s32) = G_STRICT_FSQRT [[COPY]]
212 ; CHECK-NEXT: $vgpr0 = COPY [[STRICT_FSQRT]](s32)
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 195 case ISD::STRICT_FSQRT: return "strict_fsqrt"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 124 case ISD::STRICT_FSQRT: in SoftenFloatResult()
1264 case ISD::STRICT_FSQRT: in ExpandFloatResult()
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| H A D | LegalizeDAG.cpp | 4010 case ISD::STRICT_FSQRT: in ConvertNodeToLibcall()
4863 case ISD::STRICT_FSQRT: in PromoteNode()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCTargetTransformInfo.cpp | 520 Opcode = ISD::STRICT_FSQRT; in mightUseCTR()
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| H A D | PPCISelLowering.cpp | 365 setOperationAction(ISD::STRICT_FSQRT, MVT::f32, Legal); in PPCTargetLowering()
366 setOperationAction(ISD::STRICT_FSQRT, MVT::f64, Legal); in PPCTargetLowering()
1130 setOperationAction(ISD::STRICT_FSQRT, MVT::v4f32, Legal); in PPCTargetLowering()
1144 setOperationAction(ISD::STRICT_FSQRT, MVT::v2f64, Legal); in PPCTargetLowering()
1220 setOperationAction(ISD::STRICT_FSQRT, MVT::f128, Legal); in PPCTargetLowering()
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| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 483 setOperationAction(ISD::STRICT_FSQRT, VT, Legal); in SystemZTargetLowering()
532 setOperationAction(ISD::STRICT_FSQRT, MVT::v2f64, Legal); in SystemZTargetLowering()
589 setOperationAction(ISD::STRICT_FSQRT, MVT::v4f32, Legal); in SystemZTargetLowering()
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| /llvm-project-15.0.7/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 533 def strict_fsqrt : SDNode<"ISD::STRICT_FSQRT",
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 646 setOperationAction(ISD::STRICT_FSQRT, MVT::f16, Promote); in X86TargetLowering()
758 setOperationAction(ISD::STRICT_FSQRT, MVT::f32, Legal); in X86TargetLowering()
759 setOperationAction(ISD::STRICT_FSQRT, MVT::f64, Legal); in X86TargetLowering()
806 setOperationAction(ISD::STRICT_FSQRT , MVT::f80, Legal); in X86TargetLowering()
847 setOperationAction(ISD::STRICT_FSQRT, MVT::f128, LibCall); in X86TargetLowering()
997 setOperationAction(ISD::STRICT_FSQRT, MVT::v4f32, Legal); in X86TargetLowering()
1202 setOperationAction(ISD::STRICT_FSQRT, MVT::v2f64, Legal); in X86TargetLowering()
1379 setOperationAction(ISD::STRICT_FSQRT, MVT::v8f32, Legal); in X86TargetLowering()
1705 setOperationAction(ISD::STRICT_FSQRT, MVT::v16f32, Legal); in X86TargetLowering()
1706 setOperationAction(ISD::STRICT_FSQRT, MVT::v8f64, Legal); in X86TargetLowering()
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 614 ISD::STRICT_FSQRT, ISD::STRICT_FRINT, ISD::STRICT_FNEARBYINT, in AArch64TargetLowering()
696 ISD::STRICT_FDIV, ISD::STRICT_FMA, ISD::STRICT_FSQRT}) { in AArch64TargetLowering()
963 ISD::STRICT_FSQRT, ISD::STRICT_FRINT, ISD::STRICT_FNEARBYINT, in AArch64TargetLowering()
1530 ISD::STRICT_FSQRT}) in addTypeForNEON()
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 308 ISD::STRICT_FSQRT, ISD::STRICT_FSETCC, ISD::STRICT_FSETCCS}; in RISCVTargetLowering()
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