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Searched refs:STRICT_FADD (Results 1 – 15 of 15) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dirtranslator-constrained-fp.ll11 ; CHECK-NEXT: [[STRICT_FADD:%[0-9]+]]:_(s32) = G_STRICT_FADD [[COPY]], [[COPY1]]
12 ; CHECK-NEXT: $vgpr0 = COPY [[STRICT_FADD]](s32)
25 ; CHECK-NEXT: [[STRICT_FADD:%[0-9]+]]:_(s32) = nsz G_STRICT_FADD [[COPY]], [[COPY1]]
26 ; CHECK-NEXT: $vgpr0 = COPY [[STRICT_FADD]](s32)
67 ; CHECK-NEXT: [[STRICT_FADD:%[0-9]+]]:_(s32) = G_STRICT_FADD [[COPY]], [[COPY1]]
68 ; CHECK-NEXT: $vgpr0 = COPY [[STRICT_FADD]](s32)
85 …; CHECK-NEXT: [[STRICT_FADD:%[0-9]+]]:_(<2 x s32>) = G_STRICT_FADD [[BUILD_VECTOR]], [[BUILD_VEC…
86 …; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[STRICT_FADD]](<…
125 …; CHECK-NEXT: [[STRICT_FADD:%[0-9]+]]:_(<2 x s32>) = G_STRICT_FADD [[BUILD_VECTOR]], [[BUILD_VEC…
126 …; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[STRICT_FADD]](<…
/llvm-project-15.0.7/llvm/docs/
H A DAddingConstrainedIntrinsics.rst29 node FADD must be STRICT_FADD.
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h400 STRICT_FADD, enumerator
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp2438 Slow = DAG.getNode(ISD::STRICT_FADD, dl, { DestVT, MVT::Other }, in ExpandLegalINT_TO_FP()
2460 Node->isStrictFPOpcode() ? ISD::STRICT_FADD : ISD::FADD, DestVT)) in ExpandLegalINT_TO_FP()
2523 SDValue Result = DAG.getNode(ISD::STRICT_FADD, dl, { DestVT, MVT::Other }, in ExpandLegalINT_TO_FP()
3873 ISD::STRICT_FADD, Node->getValueType(0)) != TargetLowering::Legal) in ExpandNode()
3879 SDValue Fadd = DAG.getNode(ISD::STRICT_FADD, dl, Node->getVTList(), in ExpandNode()
4202 case ISD::STRICT_FADD: in ConvertNodeToLibcall()
4762 case ISD::STRICT_FADD: in PromoteNode()
H A DSelectionDAGDumper.cpp258 case ISD::STRICT_FADD: return "strict_fadd"; in getOperationName()
H A DLegalizeFloatTypes.cpp76 case ISD::STRICT_FADD: in SoftenFloatResult()
1220 case ISD::STRICT_FADD: in ExpandFloatResult()
1753 Lo = DAG.getNode(ISD::STRICT_FADD, dl, DAG.getVTList(VT, MVT::Other), in ExpandFloatRes_XINT_TO_FP()
H A DLegalizeVectorOps.cpp1403 DAG.getNode(ISD::STRICT_FADD, DL, {Node->getValueType(0), MVT::Other}, in ExpandUINT_TO_FLOAT()
H A DSelectionDAGBuilder.cpp7331 Opcode = ISD::STRICT_FADD; in visitConstrainedFPIntrinsic()
H A DDAGCombiner.cpp1754 case ISD::STRICT_FADD: return visitSTRICT_FADD(N); in visit()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp478 setOperationAction(ISD::STRICT_FADD, VT, Legal); in SystemZTargetLowering()
527 setOperationAction(ISD::STRICT_FADD, MVT::v2f64, Legal); in SystemZTargetLowering()
584 setOperationAction(ISD::STRICT_FADD, MVT::v4f32, Legal); in SystemZTargetLowering()
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td521 def strict_fadd : SDNode<"ISD::STRICT_FADD",
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp637 setOperationAction(ISD::STRICT_FADD, MVT::f16, Promote); in X86TargetLowering()
748 setOperationAction(ISD::STRICT_FADD, MVT::f32, Legal); in X86TargetLowering()
749 setOperationAction(ISD::STRICT_FADD, MVT::f64, Legal); in X86TargetLowering()
802 setOperationAction(ISD::STRICT_FADD , MVT::f80, Legal); in X86TargetLowering()
826 setOperationAction(ISD::STRICT_FADD, MVT::f128, LibCall); in X86TargetLowering()
993 setOperationAction(ISD::STRICT_FADD, MVT::v4f32, Legal); in X86TargetLowering()
1203 setOperationAction(ISD::STRICT_FADD, MVT::v2f64, Legal); in X86TargetLowering()
1371 setOperationAction(ISD::STRICT_FADD, MVT::v8f32, Legal); in X86TargetLowering()
1697 setOperationAction(ISD::STRICT_FADD, MVT::v16f32, Legal); in X86TargetLowering()
1698 setOperationAction(ISD::STRICT_FADD, MVT::v8f64, Legal); in X86TargetLowering()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp343 setOperationAction(ISD::STRICT_FADD, MVT::f32, Legal); in PPCTargetLowering()
349 setOperationAction(ISD::STRICT_FADD, MVT::f64, Legal); in PPCTargetLowering()
1125 setOperationAction(ISD::STRICT_FADD, MVT::v4f32, Legal); in PPCTargetLowering()
1139 setOperationAction(ISD::STRICT_FADD, MVT::v2f64, Legal); in PPCTargetLowering()
1215 setOperationAction(ISD::STRICT_FADD, MVT::f128, Legal); in PPCTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp611 ISD::FMINIMUM, ISD::FMAXIMUM, ISD::STRICT_FADD, in AArch64TargetLowering()
695 for (auto Op : {ISD::STRICT_FADD, ISD::STRICT_FSUB, ISD::STRICT_FMUL, in AArch64TargetLowering()
960 ISD::FMINIMUM, ISD::FMAXIMUM, ISD::STRICT_FADD, in AArch64TargetLowering()
1528 ISD::STRICT_FMAXNUM, ISD::STRICT_FADD, ISD::STRICT_FSUB, in addTypeForNEON()
15008 case ISD::STRICT_FADD: in hasPairwiseAdd()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp306 ISD::STRICT_LLROUND, ISD::STRICT_FMA, ISD::STRICT_FADD, in RISCVTargetLowering()