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/llvm-project-15.0.7/mlir/test/Integration/Dialect/SparseTensor/CPU/
H A Dsparse_tensor_ops.mlir7 #ST1 = #sparse_tensor.encoding<{dimLevelType = ["compressed", "compressed", "compressed"]}>
24 func.func @tensor_scale(%arga: tensor<?x?x?xf64, #ST1>) -> tensor<?x?x?xf64, #ST2> {
29 %d0 = tensor.dim %arga, %c0 : tensor<?x?x?xf64, #ST1>
30 %d1 = tensor.dim %arga, %c1 : tensor<?x?x?xf64, #ST1>
31 %d2 = tensor.dim %arga, %c2 : tensor<?x?x?xf64, #ST1>
34 ins(%arga: tensor<?x?x?xf64, #ST1>)
62 %st = sparse_tensor.convert %t : tensor<3x4x8xf64> to tensor<?x?x?xf64, #ST1>
65 %0 = call @tensor_scale(%st) : (tensor<?x?x?xf64, #ST1>) -> tensor<?x?x?xf64, #ST2>
71 %m1 = sparse_tensor.values %st : tensor<?x?x?xf64, #ST1> to memref<?xf64>
79 bufferization.dealloc_tensor %st : tensor<?x?x?xf64, #ST1>
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dhelloworld.ll4 …-gnu -march=mipsel -mattr=mips16 -relocation-model=static -O3 < %s | FileCheck %s -check-prefix=ST1
43 ; ST1: li ${{[0-9]+}}, %hi($.str)
44 ; ST1: sll ${{[0-9]+}}, ${{[0-9]+}}, 16
45 ; ST1: addiu ${{[0-9]+}}, %lo($.str)
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dmultiple-uses-load-bitcast-select.ll12 ; CHECK-NEXT: [[TMP1:%.*]] = bitcast i64* [[ST1:%.*]] to double*
/llvm-project-15.0.7/llvm/docs/
H A DBigEndianNEON.rst109 …age over ``LD1`` and ``ST1``. ``LDR`` and ``STR`` are oblivious to the size of the individual lane…
152 …` was chosen as the canonical vector load instruction (and by inference, ``ST1`` for vector stores…
179 …ence such as that in the figure on the right. The mismatched ``LD1`` and ``ST1`` cause the stored …
200 ST1 v0.2d, [y]
H A DWritingAnLLVMBackend.rst1539 assigned to the register ``ST0`` or ``ST1``, the ``RetCC_X86Common`` is
1545 CCIfType<[f32], CCAssignToReg<[ST0, ST1]>>,
1546 CCIfType<[f64], CCAssignToReg<[ST0, ST1]>>,
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dmerge-store-partially-alias-loads.ll24 ; DBGDAG-DAG: [[ST1:t[0-9]+]]: ch = store<(store (s8) into %ir.tmp14)> [[ENTRYTOKEN]], [[LD1]], t{{…
/llvm-project-15.0.7/llvm/unittests/tools/llvm-exegesis/X86/
H A DTargetTest.cpp306 const MCInst CopySt0ToSt1 = MCInstBuilder(X86::ST_Frr).addReg(X86::ST1); in TEST_F()
307 EXPECT_THAT(setRegTo(X86::ST1, APInt(32, 0x11112222ULL)), in TEST_F()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86Instr3DNow.td78 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7] in
H A DX86InstrInfo.td3483 def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>;
3484 def: InstAlias<"fadd", (ADD_FPrST0 ST1), 0>;
3485 def : InstAlias<"fsub{|r}p", (SUBR_FPrST0 ST1), 0>;
3486 def : InstAlias<"fsub{r|}p", (SUB_FPrST0 ST1), 0>;
3487 def : InstAlias<"fmul", (MUL_FPrST0 ST1), 0>;
3488 def : InstAlias<"fmulp", (MUL_FPrST0 ST1), 0>;
3489 def : InstAlias<"fdiv{|r}p", (DIVR_FPrST0 ST1), 0>;
3490 def : InstAlias<"fdiv{r|}p", (DIV_FPrST0 ST1), 0>;
3491 def : InstAlias<"fxch", (XCH_F ST1), 0>;
3492 def : InstAlias<"fcom", (COM_FST0r ST1), 0>;
[all …]
H A DX86InstrControl.td20 // ST1 arguments when returning values on the x87 stack.
H A DX86InstrMMX.td153 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7] in
H A DX86RegisterInfo.td296 def ST1 : X86Reg<"st(1)", 1>, DwarfRegNum<[34, 13, 12]>;
H A DX86InstrCompiler.td458 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7,
478 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7,
/llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp207 {codeview::RegisterId::ST1, X86::ST1}, in initLLVMToSEHAndCVRegMapping()
216 {codeview::RegisterId::ST1, X86::FP1}, in initLLVMToSEHAndCVRegMapping()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SchedFalkorDetails.td993 …(instregex "^ST1(One(v8b|v4h|v2s|v1d)|(i8|i16|i32|i64)|One(v16b|v8h|v4s|v2d)|Two(v8b|v4h|v2s|v1d))…
995 … (instregex "^ST1(One(v8b|v4h|v2s|v1d)_POST|(i8|i16|i32|i64)_POST)$")>;
999 … (instregex "^ST1(One(v16b|v8h|v4s|v2d)|Two(v8b|v4h|v2s|v1d))_POST$")>;
1004 … (instregex "^ST1(Two(v16b|v8h|v4s|v2d)|(Three|Four)(v8b|v4h|v2s|v1d))$")>;
1013 … (instregex "^ST1(Two(v16b|v8h|v4s|v2d)|(Three|Four)(v8b|v4h|v2s|v1d))_POST$")>;
H A DAArch64SchedKryoDetails.td1848 (instregex "ST1(One(v8b|v4h|v2s|v1d|v16b|v8h|v4s|v2d)|(i8|i16|i32|i64)|Two(v8b|v4h|v2s|v1d))$")>;
1854 …(instregex "ST1(One(v8b|v4h|v2s|v1d|v16b|v8h|v4s|v2d)|(i8|i16|i32|i64)|Two(v8b|v4h|v2s|v1d))_POST$…
1860 (instregex "ST1(One(v16b|v8h|v4s|v2d)|Two(v8b|v4h|v2s|v1d))_POST$")>;
1866 (instregex "ST1(Two(v16b|v8h|v4s|v2d)|(Three|Four)(v8b|v4h|v2s|v1d))_POST$")>;
1872 (instregex "ST1(Two(v16b|v8h|v4s|v2d)|(Three|Four)(v8b|v4h|v2s|v1d))$")>;
H A DAArch64InstrInfo.td3357 // We must use ST1 to store vectors in big-endian.
3371 // We must use ST1 to store vectors in big-endian.
3456 // We must use ST1 to store vectors in big-endian.
3483 // We must use ST1 to store vectors in big-endian.
3599 // We must use ST1 to store vectors in big-endian.
3625 // We must use ST1 to store vectors in big-endian.
6970 defm ST1 : SIMDSt1Multiple<"st1">;
7150 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn)>;
7167 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
7243 defm ST1 : SIMDLdSt1SingleAliases<"st1">;
[all …]
H A DAArch64SchedNeoverseN2.td2162 def : InstRW<[N2Write_2cyc_1L01_1V], (instregex "^ST1[BHWD]_IMM$",
2169 def : InstRW<[N2Write_2cyc_1L01_1V], (instregex "^ST1[BWD]$",
/llvm-project-15.0.7/mlir/test/Dialect/Linalg/
H A Dhoisting.mlir372 …// CHECK: %[[ST1:.*]] = tensor.extract_slice %[[TENSOR1_ARG_L2]][%[[J]],{{.*}}: tensor<?x?xf32…
373 … // CHECK: %[[V1:.*]] = vector.transfer_read %[[ST1]]{{.*}} : tensor<?x?xf32>, vector<2xf32>
/llvm-project-15.0.7/llvm/include/llvm/DebugInfo/CodeView/
H A DCodeViewRegisters.def125 CV_REGISTER(ST1, 129)
/llvm-project-15.0.7/llvm/docs/TableGen/
H A Dindex.rst72 RDX, RIP, RSI, RSP, SI, SIL, SP, SPL, ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7,
/llvm-project-15.0.7/mlir/test/Conversion/MemRefToLLVM/
H A Dmemref-to-llvm.mlir490 …// CHECK: %[[ST1:.*]] = llvm.extractvalue %{{.*}}[4, 1] : !llvm.struct<(ptr<f32>, ptr<f32>, i64, a…
497 // CHECK: %[[MUL1:.*]] = llvm.mul %[[C0]], %[[ST1]] : i64
527 …// CHECK: %[[ST1:.*]] = llvm.extractvalue %{{.*}}[4, 1] : !llvm.struct<(ptr<f32>, ptr<f32>, i64, a…
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp19116 if (StoreSDNode *ST1 = dyn_cast<StoreSDNode>(Chain)) { in visitSTORE() local
19118 ST1->isUnindexed() && ST1->isSimple()) { in visitSTORE()
19119 if (OptLevel != CodeGenOpt::None && ST1->getBasePtr() == Ptr && in visitSTORE()
19120 ST1->getValue() == Value && ST->getMemoryVT() == ST1->getMemoryVT() && in visitSTORE()
19121 ST->getAddressSpace() == ST1->getAddressSpace()) { in visitSTORE()
19127 if (OptLevel != CodeGenOpt::None && ST1->hasOneUse() && in visitSTORE()
19128 !ST1->getBasePtr().isUndef() && in visitSTORE()
19132 !ST1->getMemoryVT().isScalableVector() && in visitSTORE()
19133 ST->getAddressSpace() == ST1->getAddressSpace()) { in visitSTORE()
19137 unsigned ChainBitSize = ST1->getMemoryVT().getFixedSizeInBits(); in visitSTORE()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp1539 case 1: RegNo = X86::ST1; break; in ParseRegister()
/llvm-project-15.0.7/clang/include/clang/Basic/
H A Darm_neon.td725 def ST1 : WInst<"vst1", "v*(.!)", "dQdPlQPl">;

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