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Searched refs:SREM (Results 1 – 25 of 58) sorted by relevance

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/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dsrem-canonicalize.ll7 ; CHECK-NEXT: [[SREM:%.*]] = sub nsw i32 0, [[TMP1]]
8 ; CHECK-NEXT: ret i32 [[SREM]]
20 ; CHECK-NEXT: [[SREM:%.*]] = srem i32 [[Y]], [[NEG]]
21 ; CHECK-NEXT: ret i32 [[SREM]]
32 ; CHECK-NEXT: [[SREM:%.*]] = srem i32 [[NEG]], [[Y:%.*]]
33 ; CHECK-NEXT: ret i32 [[SREM]]
43 ; CHECK-NEXT: [[SREM:%.*]] = sub nsw <2 x i32> zeroinitializer, [[TMP1]]
44 ; CHECK-NEXT: ret <2 x i32> [[SREM]]
54 ; CHECK-NEXT: [[SREM:%.*]] = srem i32 [[NEG]], [[Y:%.*]]
55 ; CHECK-NEXT: [[SREM2:%.*]] = srem i32 [[SREM]], [[NEG]]
H A Dashr-demand.ll8 ; CHECK-NEXT: [[SREM:%.*]] = srem i32 [[A0:%.*]], 2
9 ; CHECK-NEXT: [[MASK:%.*]] = and i32 [[SREM]], 2
34 ; CHECK-NEXT: [[SREM:%.*]] = srem <2 x i32> [[A0:%.*]], <i32 2, i32 2>
35 ; CHECK-NEXT: [[MASK:%.*]] = and <2 x i32> [[SREM]], <i32 2, i32 2>
46 ; CHECK-NEXT: [[SREM:%.*]] = srem <2 x i32> [[A0:%.*]], <i32 2, i32 2>
47 ; CHECK-NEXT: [[MASK:%.*]] = and <2 x i32> [[SREM]], <i32 2, i32 2>
/llvm-project-15.0.7/llvm/test/CodeGen/X86/GlobalISel/
H A Dx86_64-legalize-srem.mir77 ; CHECK: [[SREM:%[0-9]+]]:_(s8) = G_SREM [[TRUNC]], [[TRUNC1]]
78 ; CHECK: $al = COPY [[SREM]](s8)
136 ; CHECK: [[SREM:%[0-9]+]]:_(s16) = G_SREM [[TRUNC]], [[TRUNC1]]
137 ; CHECK: $ax = COPY [[SREM]](s16)
191 ; CHECK: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[COPY]], [[COPY1]]
192 ; CHECK: $eax = COPY [[SREM]](s32)
244 ; CHECK: [[SREM:%[0-9]+]]:_(s64) = G_SREM [[COPY]], [[COPY1]]
245 ; CHECK: $rax = COPY [[SREM]](s64)
H A Dx86-legalize-srem.mir76 ; CHECK: [[SREM:%[0-9]+]]:_(s8) = G_SREM [[LOAD]], [[LOAD1]]
77 ; CHECK: $al = COPY [[SREM]](s8)
138 ; CHECK: [[SREM:%[0-9]+]]:_(s16) = G_SREM [[LOAD]], [[LOAD1]]
139 ; CHECK: $ax = COPY [[SREM]](s16)
200 ; CHECK: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[LOAD]], [[LOAD1]]
201 ; CHECK: $eax = COPY [[SREM]](s32)
H A Dx86_64-irtranslator.ll208 ; CHECK: [[SREM:%[0-9]+]]:_(s8) = G_SREM [[TRUNC]], [[TRUNC1]]
209 ; CHECK: $al = COPY [[SREM]](s8)
223 ; CHECK: [[SREM:%[0-9]+]]:_(s16) = G_SREM [[TRUNC]], [[TRUNC1]]
224 ; CHECK: $ax = COPY [[SREM]](s16)
236 ; CHECK: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[COPY]], [[COPY1]]
237 ; CHECK: $eax = COPY [[SREM]](s32)
249 ; CHECK: [[SREM:%[0-9]+]]:_(s64) = G_SREM [[COPY]], [[COPY1]]
250 ; CHECK: $rax = COPY [[SREM]](s64)
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/
H A Drem_and_div.mir47 ; MIPS32: [[SREM:%[0-9]+]]:gprb(s32) = G_SREM [[COPY1]], [[COPY]]
48 ; MIPS32: $v0 = COPY [[SREM]](s32)
H A Drem_and_div_vec.mir158 ; P5600: [[SREM:%[0-9]+]]:fprb(<16 x s8>) = G_SREM [[LOAD]], [[LOAD1]]
159 ; P5600: G_STORE [[SREM]](<16 x s8>), [[COPY2]](p0) :: (store (<16 x s8>) into %ir.c)
187 ; P5600: [[SREM:%[0-9]+]]:fprb(<8 x s16>) = G_SREM [[LOAD]], [[LOAD1]]
188 ; P5600: G_STORE [[SREM]](<8 x s16>), [[COPY2]](p0) :: (store (<8 x s16>) into %ir.c)
216 ; P5600: [[SREM:%[0-9]+]]:fprb(<4 x s32>) = G_SREM [[LOAD]], [[LOAD1]]
217 ; P5600: G_STORE [[SREM]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
245 ; P5600: [[SREM:%[0-9]+]]:fprb(<2 x s64>) = G_SREM [[LOAD]], [[LOAD1]]
246 ; P5600: G_STORE [[SREM]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
H A Drem_and_div_vec.mir153 ; P5600: [[SREM:%[0-9]+]]:_(<16 x s8>) = G_SREM [[LOAD]], [[LOAD1]]
154 ; P5600: G_STORE [[SREM]](<16 x s8>), [[COPY2]](p0) :: (store (<16 x s8>) into %ir.c)
181 ; P5600: [[SREM:%[0-9]+]]:_(<8 x s16>) = G_SREM [[LOAD]], [[LOAD1]]
182 ; P5600: G_STORE [[SREM]](<8 x s16>), [[COPY2]](p0) :: (store (<8 x s16>) into %ir.c)
209 ; P5600: [[SREM:%[0-9]+]]:_(<4 x s32>) = G_SREM [[LOAD]], [[LOAD1]]
210 ; P5600: G_STORE [[SREM]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
237 ; P5600: [[SREM:%[0-9]+]]:_(<2 x s64>) = G_SREM [[LOAD]], [[LOAD1]]
238 ; P5600: G_STORE [[SREM]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
H A Drem_and_div_vec_builtin.mir181 ; P5600: [[SREM:%[0-9]+]]:_(<16 x s8>) = G_SREM [[LOAD]], [[LOAD1]]
182 ; P5600: G_STORE [[SREM]](<16 x s8>), [[COPY2]](p0) :: (store (<16 x s8>) into %ir.c)
209 ; P5600: [[SREM:%[0-9]+]]:_(<8 x s16>) = G_SREM [[LOAD]], [[LOAD1]]
210 ; P5600: G_STORE [[SREM]](<8 x s16>), [[COPY2]](p0) :: (store (<8 x s16>) into %ir.c)
237 ; P5600: [[SREM:%[0-9]+]]:_(<4 x s32>) = G_SREM [[LOAD]], [[LOAD1]]
238 ; P5600: G_STORE [[SREM]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
265 ; P5600: [[SREM:%[0-9]+]]:_(<2 x s64>) = G_SREM [[LOAD]], [[LOAD1]]
266 ; P5600: G_STORE [[SREM]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
H A Drem_and_div.mir165 ; MIPS32: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[ASHR]], [[ASHR1]]
166 ; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[SREM]], [[C]](s32)
197 ; MIPS32: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[ASHR]], [[ASHR1]]
198 ; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[SREM]], [[C]](s32)
224 ; MIPS32: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[COPY1]], [[COPY]]
225 ; MIPS32: $v0 = COPY [[SREM]](s32)
/llvm-project-15.0.7/llvm/test/Transforms/TypePromotion/ARM/
H A Dsigned.ll51 ; CHECK-NEXT: [[SREM:%.*]] = srem i16 [[ARG:%.*]], 4
52 ; CHECK-NEXT: [[CMP:%.*]] = icmp ne i16 [[SREM]], 0
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dsdiv-pow2-arm-size.ll4 ; Check SREM
H A Ddivmod-eabi.ll12 ; All "eabi" (Bare, GNU and Android) must lower SREM/UREM to __aeabi_{u,i}divmod
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp1343 { ISD::SREM, MVT::v1i64, 1 * FunctionCallDivCost}, in getArithmeticInstrCost()
1347 { ISD::SREM, MVT::v2i32, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
1351 { ISD::SREM, MVT::v4i16, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
1355 { ISD::SREM, MVT::v8i8, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
1360 { ISD::SREM, MVT::v2i64, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
1364 { ISD::SREM, MVT::v4i32, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
1368 { ISD::SREM, MVT::v8i16, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
1372 { ISD::SREM, MVT::v16i8, 16 * FunctionCallDivCost}, in getArithmeticInstrCost()
1927 case ISD::SREM: in maybeLoweredToCall()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp253 if ((ISD == ISD::SDIV || ISD == ISD::SREM) && in getArithmeticInstrCost()
268 if (ISD == ISD::SREM) { in getArithmeticInstrCost()
380 { ISD::SREM, MVT::v16i32, 8 }, // pmuludq+mul+sub sequence in getArithmeticInstrCost()
400 { ISD::SREM, MVT::v8i32, 8 }, // pmuludq+mul+sub sequence in getArithmeticInstrCost()
424 { ISD::SREM, MVT::v4i32, 8 }, // pmuludq+mul+sub sequence in getArithmeticInstrCost()
445 { ISD::SREM, MVT::v32i16, 8 }, // vpmulhw+mul+sub sequence in getArithmeticInstrCost()
460 { ISD::SREM, MVT::v16i32, 17 }, // vpmuldq+mul+sub sequence in getArithmeticInstrCost()
468 { ISD::SREM, MVT::v32i16, 16 }, // 2*vpmulhw+mul+sub sequence in getArithmeticInstrCost()
487 { ISD::SREM, MVT::v16i16, 8 }, // vpmulhw+mul+sub sequence in getArithmeticInstrCost()
491 { ISD::SREM, MVT::v8i32, 19 }, // vpmuldq+mul+sub sequence in getArithmeticInstrCost()
[all …]
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h244 SREM, enumerator
H A DBasicTTIImpl.h826 if (ISD == ISD::UREM || ISD == ISD::SREM) {
827 bool IsSigned = ISD == ISD::SREM;
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp1923 case ISD::SREM: in selectDivRem()
1944 unsigned MFOpc = (ISDOpcode == ISD::SREM || ISDOpcode == ISD::UREM) in selectDivRem()
2045 if (!selectBinaryOp(I, ISD::SREM)) in fastSelectInstruction()
2046 return selectDivRem(I, ISD::SREM); in fastSelectInstruction()
H A DMipsSEISelLowering.cpp235 setOperationAction(ISD::SREM, MVT::i32, Legal); in MipsSETargetLowering()
282 setOperationAction(ISD::SREM, MVT::i64, Legal); in MipsSETargetLowering()
333 setOperationAction(ISD::SREM, Ty, Legal); in addMSAIntType()
2049 return DAG.getNode(ISD::SREM, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp322 case ISD::SREM: in LegalizeOp()
905 case ISD::SREM: in Expand()
1559 assert((Node->getOpcode() == ISD::SREM || Node->getOpcode() == ISD::UREM) && in ExpandREM()
H A DSelectionDAGBuilder.h499 void visitSRem(const User &I) { visitBinary(I, ISD::SREM); } in visitSRem()
H A DSelectionDAGDumper.cpp241 case ISD::SREM: return "srem"; in getOperationName()
/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp137 setOperationAction(ISD::SREM, MVT::i8, Promote); in MSP430TargetLowering()
143 setOperationAction(ISD::SREM, MVT::i16, LibCall); in MSP430TargetLowering()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp931 case ISD::SREM: in canOpTrap()
1798 case SRem: return ISD::SREM; in InstructionOpcodeToISD()
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp105 setOperationAction(ISD::SREM, VT, Expand); in BPFTargetLowering()

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