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/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dregbankselect-smin.mir18 ; CHECK-NEXT: [[SMIN:%[0-9]+]]:sgpr(s32) = G_SMIN [[COPY]], [[COPY1]]
19 ; CHECK-NEXT: $sgpr0 = COPY [[SMIN]](s32)
41 ; CHECK-NEXT: $vgpr0 = COPY [[SMIN]](s32)
63 ; CHECK-NEXT: $vgpr0 = COPY [[SMIN]](s32)
84 ; CHECK-NEXT: $vgpr0 = COPY [[SMIN]](s32)
106 ; CHECK-NEXT: $vgpr0 = COPY [[SMIN]](s32)
131 ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC [[SMIN]](s32)
162 ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC [[SMIN]](s32)
221 ; CHECK-NEXT: $vgpr0 = COPY [[SMIN]](<2 x s16>)
243 ; CHECK-NEXT: $vgpr0 = COPY [[SMIN]](<2 x s16>)
[all …]
H A Dlegalize-smin.mir19 ; SI-NEXT: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[COPY]], [[COPY1]]
20 ; SI-NEXT: $vgpr0 = COPY [[SMIN]](s32)
26 ; VI-NEXT: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[COPY]], [[COPY1]]
27 ; VI-NEXT: $vgpr0 = COPY [[SMIN]](s32)
34 ; GFX9-NEXT: $vgpr0 = COPY [[SMIN]](s32)
91 ; SI-NEXT: $vgpr0 = COPY [[SMIN]](s32)
135 ; SI-NEXT: $vgpr0 = COPY [[SMIN]](s32)
186 ; SI-NEXT: $vgpr0 = COPY [[SMIN]](s32)
195 ; VI-NEXT: $vgpr0 = COPY [[SMIN]](s32)
204 ; GFX9-NEXT: $vgpr0 = COPY [[SMIN]](s32)
[all …]
H A Dlegalize-saddsat.mir27 ; GFX6-NEXT: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SHL]], [[C3]]
28 ; GFX6-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[SMIN]]
49 ; GFX8-NEXT: [[SMIN:%[0-9]+]]:_(s16) = G_SMIN [[SHL]], [[C3]]
50 ; GFX8-NEXT: [[SUB1:%[0-9]+]]:_(s16) = G_SUB [[C2]], [[SMIN]]
99 ; GFX6-NEXT: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SHL]], [[C3]]
100 ; GFX6-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[SMIN]]
121 ; GFX8-NEXT: [[SMIN:%[0-9]+]]:_(s16) = G_SMIN [[SHL]], [[C3]]
122 ; GFX8-NEXT: [[SUB1:%[0-9]+]]:_(s16) = G_SUB [[C2]], [[SMIN]]
174 ; GFX6-NEXT: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SHL]], [[C4]]
175 ; GFX6-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[SMIN]]
[all …]
H A Dlegalize-ssubsat.mir27 ; GFX6-NEXT: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SHL]], [[C3]]
28 ; GFX6-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[SMIN]], [[C2]]
49 ; GFX8-NEXT: [[SMIN:%[0-9]+]]:_(s16) = G_SMIN [[SHL]], [[C3]]
50 ; GFX8-NEXT: [[SUB1:%[0-9]+]]:_(s16) = G_SUB [[SMIN]], [[C2]]
99 ; GFX6-NEXT: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SHL]], [[C3]]
100 ; GFX6-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[SMIN]], [[C2]]
121 ; GFX8-NEXT: [[SMIN:%[0-9]+]]:_(s16) = G_SMIN [[SHL]], [[C3]]
122 ; GFX8-NEXT: [[SUB1:%[0-9]+]]:_(s16) = G_SUB [[SMIN]], [[C2]]
174 ; GFX6-NEXT: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SHL]], [[C4]]
175 ; GFX6-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[SMIN]], [[C3]]
[all …]
H A Dlegalize-fptrunc.mir129 ; CHECK-NEXT: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SMAX]], [[C11]]
132 ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[OR4]], [[SMIN]](s32)
133 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR2]], [[SMIN]](s32)
210 ; CHECK-NEXT: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SMAX]], [[C11]]
213 ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[OR4]], [[SMIN]](s32)
214 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR2]], [[SMIN]](s32)
337 ; CHECK-NEXT: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SMAX]], [[C11]]
340 ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[OR4]], [[SMIN]](s32)
341 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR2]], [[SMIN]](s32)
418 ; CHECK-NEXT: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SMAX]], [[C11]]
[all …]
H A Dregbankcombiner-smed3.mir271 ; CHECK-NEXT: [[SMIN:%[0-9]+]]:vgpr(<2 x s16>) = G_SMIN [[COPY1]], [[COPY]]
273 ; CHECK-NEXT: [[SMAX:%[0-9]+]]:vgpr(<2 x s16>) = G_SMAX [[COPY2]], [[SMIN]]
305 ; CHECK-NEXT: [[SMIN:%[0-9]+]]:sgpr(s32) = G_SMIN [[SMAX]], [[C1]]
306 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[SMIN]](s32)
/llvm-project-15.0.7/llvm/test/Transforms/IRCE/
H A Drc-negative-bound.ll118 ; CHECK-NEXT: [[SMIN:%.*]] = call i32 @llvm.smin.i32(i32 [[BOUND]], i32 0)
119 ; CHECK-NEXT: [[SMAX1:%.*]] = call i32 @llvm.smax.i32(i32 [[SMIN]], i32 -1)
204 ; CHECK-NEXT: [[SMIN:%.*]] = call i32 @llvm.smin.i32(i32 [[BOUND:%.*]], i32 0)
205 ; CHECK-NEXT: [[TMP0:%.*]] = sub i32 [[BOUND]], [[SMIN]]
206 ; CHECK-NEXT: [[SMAX:%.*]] = call i32 @llvm.smax.i32(i32 [[SMIN]], i32 -1)
398 ; CHECK-NEXT: [[SMIN:%.*]] = call i32 @llvm.smin.i32(i32 [[BOUND]], i32 0)
399 ; CHECK-NEXT: [[SMAX1:%.*]] = call i32 @llvm.smax.i32(i32 [[SMIN]], i32 -1)
486 ; CHECK-NEXT: [[SMIN:%.*]] = call i32 @llvm.smin.i32(i32 [[BOUND:%.*]], i32 0)
487 ; CHECK-NEXT: [[TMP0:%.*]] = sub i32 [[BOUND]], [[SMIN]]
488 ; CHECK-NEXT: [[SMAX:%.*]] = call i32 @llvm.smax.i32(i32 [[SMIN]], i32 -1)
H A Dconjunctive-checks.ll13 ; CHECK-NEXT: [[SMIN:%.*]] = call i32 @llvm.smin.i32(i32 [[N]], i32 [[TMP0]])
14 ; CHECK-NEXT: [[EXIT_MAINLOOP_AT:%.*]] = call i32 @llvm.smax.i32(i32 [[SMIN]], i32 0)
104 ; CHECK-NEXT: [[SMIN:%.*]] = call i32 @llvm.smin.i32(i32 [[LEN_B]], i32 [[LEN_A]])
105 ; CHECK-NEXT: [[SMIN1:%.*]] = call i32 @llvm.smin.i32(i32 [[SMIN]], i32 [[N]])
H A Dmultiple-access-no-preloop.ll13 ; CHECK-NEXT: [[SMIN:%.*]] = call i32 @llvm.smin.i32(i32 [[LEN_B]], i32 [[LEN_A]])
14 ; CHECK-NEXT: [[SMIN1:%.*]] = call i32 @llvm.smin.i32(i32 [[SMIN]], i32 [[N]])
H A Dnon-loop-invariant-rhs-instr.ll13 ; CHECK-NEXT: [[SMIN:%.*]] = call i64 @llvm.smin.i64(i64 [[LEN]], i64 0)
14 ; CHECK-NEXT: [[TMP2:%.*]] = sub i64 [[LEN]], [[SMIN]]
H A Dranges_of_different_types.ll26 ; CHECK-NEXT: [[SMIN:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP0]], i32 101)
27 ; CHECK-NEXT: [[EXIT_MAINLOOP_AT:%.*]] = call i32 @llvm.smax.i32(i32 [[SMIN]], i32 0)
244 ; CHECK-NEXT: [[SMIN:%.*]] = call i32 @llvm.smin.i32(i32 [[LEN]], i32 13)
245 ; CHECK-NEXT: [[TMP0:%.*]] = sub i32 [[LEN]], [[SMIN]]
447 ; CHECK-NEXT: [[SMIN:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP0]], i32 101)
448 ; CHECK-NEXT: [[EXIT_MAINLOOP_AT:%.*]] = call i32 @llvm.smax.i32(i32 [[SMIN]], i32 0)
635 ; CHECK-NEXT: [[SMIN:%.*]] = call i32 @llvm.smin.i32(i32 [[LEN]], i32 13)
636 ; CHECK-NEXT: [[TMP0:%.*]] = sub i32 [[LEN]], [[SMIN]]
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp3356 ISD = ISD::SMIN; in getTypeBasedIntrinsicInstrCost()
4553 {ISD::SMIN, MVT::v8i16, 1}, in getMinMaxCost()
4558 {ISD::SMIN, MVT::v4i32, 1}, in getMinMaxCost()
4561 {ISD::SMIN, MVT::v16i8, 1}, in getMinMaxCost()
4571 {ISD::SMIN, MVT::v8i32, 3}, in getMinMaxCost()
4573 {ISD::SMIN, MVT::v16i16, 3}, in getMinMaxCost()
4696 {ISD::SMIN, MVT::v16i8, 6}, in getMinMaxReductionCost()
4704 {ISD::SMIN, MVT::v16i16, 6}, in getMinMaxReductionCost()
4706 {ISD::SMIN, MVT::v32i8, 8}, in getMinMaxReductionCost()
4711 {ISD::SMIN, MVT::v32i16, 8}, in getMinMaxReductionCost()
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dvec_minmax_match.ll162 ; (X <s C1) ? C1 : SMIN(X, C2) ==> SMAX(SMIN(X, C2), C1)
177 ; (X >s C1) ? C1 : SMAX(X, C2) ==> SMIN(SMAX(X, C2), C1)
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dicmp-div-constant.ll312 ; negative test - must be SMIN
325 ; negative test - must be SMIN
338 ; negative test - must be SMIN
H A Dminmax-fold.ll214 ; SMIN(SMIN(X, 11), 92) -> SMIN(X, 11)
278 ; SMIN(SMIN(X, 92), 11) -> SMIN(X, 11)
346 ; (X <s C1) ? C1 : SMIN(X, C2) ==> SMAX(SMIN(X, C2), C1)
361 ; (X >s C1) ? C1 : SMAX(X, C2) ==> SMIN(SMAX(X, C2), C1)
376 ; (X >s C1) ? SMIN(X, C2) : C1 ==> SMAX(SMIN(X, C2), C1)
391 ; (X <s C1) ? SMAX(X, C2) : C1 ==> SMIN(SMAX(X, C1), C2)
H A Dselect_meta.ll160 ; SMIN(SMIN(X, 92), 11) -> SMIN(X, 11)
H A Drem.ll893 ; SMIN % -1 element is poison.
999 ; There's no unsigned equivalent to "SMIN % -1", so this is just the usual constant folding.
/llvm-project-15.0.7/llvm/test/Transforms/HardwareLoops/ARM/
H A Dsimple-do.ll151 ; CHECK: [[SMIN:%[^ ]+]] = call i32 @llvm.smin.i32(i32 %n, i32 2)
152 ; CHECK: [[SUB:%[^ ]+]] = sub i32 [[ROUND]], [[SMIN]]
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h660 SMIN, enumerator
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dlegalize-min-max.mir60 ; CHECK: [[SMIN:%[0-9]+]]:_(<16 x s8>) = G_SMIN [[BUILD_VECTOR]], [[BUILD_VECTOR2]]
63 ; CHECK: G_STORE [[SMIN]](<16 x s8>), [[COPY]](p0) :: (store (<16 x s8>), align 32)
130 ; CHECK: [[SMIN:%[0-9]+]]:_(<8 x s16>) = G_SMIN [[BUILD_VECTOR]], [[BUILD_VECTOR2]]
133 ; CHECK: G_STORE [[SMIN]](<8 x s16>), [[COPY]](p0) :: (store (<8 x s16>), align 32)
200 ; CHECK: [[SMIN:%[0-9]+]]:_(<4 x s32>) = G_SMIN [[BUILD_VECTOR]], [[BUILD_VECTOR2]]
203 ; CHECK: G_STORE [[SMIN]](<4 x s32>), [[COPY]](p0) :: (store (<4 x s32>), align 32)
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp391 case ISD::SMIN: in LegalizeOp()
820 case ISD::SMIN: in Expand()
H A DSelectionDAGDumper.cpp276 case ISD::SMIN: return "smin"; in getOperationName()
/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp122 setOperationAction(ISD::SMIN, MVT::i32, Legal); in ARCTargetLowering()
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/AArch64/
H A Dscalable-reductions.ll128 ; SMIN
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/RISCV/
H A Dscalable-reductions.ll131 ; SMIN

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