Lines Matching refs:SMIN

2922     { ISD::SMIN,       MVT::v32i16,  1 },  in getTypeBasedIntrinsicInstrCost()
2923 { ISD::SMIN, MVT::v64i8, 1 }, in getTypeBasedIntrinsicInstrCost()
2967 { ISD::SMIN, MVT::v8i64, 1 }, in getTypeBasedIntrinsicInstrCost()
2968 { ISD::SMIN, MVT::v16i32, 1 }, in getTypeBasedIntrinsicInstrCost()
2969 { ISD::SMIN, MVT::v32i16, 2 }, in getTypeBasedIntrinsicInstrCost()
2970 { ISD::SMIN, MVT::v64i8, 2 }, in getTypeBasedIntrinsicInstrCost()
2971 { ISD::SMIN, MVT::v4i64, 1 }, in getTypeBasedIntrinsicInstrCost()
2972 { ISD::SMIN, MVT::v2i64, 1 }, in getTypeBasedIntrinsicInstrCost()
3069 { ISD::SMIN, MVT::v8i32, 1 }, in getTypeBasedIntrinsicInstrCost()
3070 { ISD::SMIN, MVT::v16i16, 1 }, in getTypeBasedIntrinsicInstrCost()
3071 { ISD::SMIN, MVT::v32i8, 1 }, in getTypeBasedIntrinsicInstrCost()
3124 { ISD::SMIN, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert in getTypeBasedIntrinsicInstrCost()
3125 { ISD::SMIN, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert in getTypeBasedIntrinsicInstrCost()
3126 { ISD::SMIN, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert in getTypeBasedIntrinsicInstrCost()
3176 { ISD::SMIN, MVT::v4i32, 1 }, in getTypeBasedIntrinsicInstrCost()
3177 { ISD::SMIN, MVT::v16i8, 1 }, in getTypeBasedIntrinsicInstrCost()
3234 { ISD::SMIN, MVT::v8i16, 1 }, in getTypeBasedIntrinsicInstrCost()
3356 ISD = ISD::SMIN; in getTypeBasedIntrinsicInstrCost()
4540 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; in getMinMaxCost()
4553 {ISD::SMIN, MVT::v8i16, 1}, in getMinMaxCost()
4558 {ISD::SMIN, MVT::v4i32, 1}, in getMinMaxCost()
4561 {ISD::SMIN, MVT::v16i8, 1}, in getMinMaxCost()
4571 {ISD::SMIN, MVT::v8i32, 3}, in getMinMaxCost()
4573 {ISD::SMIN, MVT::v16i16, 3}, in getMinMaxCost()
4575 {ISD::SMIN, MVT::v32i8, 3}, in getMinMaxCost()
4580 {ISD::SMIN, MVT::v8i32, 1}, in getMinMaxCost()
4582 {ISD::SMIN, MVT::v16i16, 1}, in getMinMaxCost()
4584 {ISD::SMIN, MVT::v32i8, 1}, in getMinMaxCost()
4591 {ISD::SMIN, MVT::v2i64, 1}, in getMinMaxCost()
4593 {ISD::SMIN, MVT::v4i64, 1}, in getMinMaxCost()
4595 {ISD::SMIN, MVT::v8i64, 1}, in getMinMaxCost()
4597 {ISD::SMIN, MVT::v16i32, 1}, in getMinMaxCost()
4602 {ISD::SMIN, MVT::v32i16, 1}, in getMinMaxCost()
4604 {ISD::SMIN, MVT::v64i8, 1}, in getMinMaxCost()
4670 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; in getMinMaxReductionCost()
4687 {ISD::SMIN, MVT::v2i16, 3}, // same as sse2 in getMinMaxReductionCost()
4688 {ISD::SMIN, MVT::v4i16, 5}, // same as sse2 in getMinMaxReductionCost()
4691 {ISD::SMIN, MVT::v8i16, 4}, // phminposuw+xor in getMinMaxReductionCost()
4693 {ISD::SMIN, MVT::v2i8, 3}, // pminsb in getMinMaxReductionCost()
4694 {ISD::SMIN, MVT::v4i8, 5}, // pminsb in getMinMaxReductionCost()
4695 {ISD::SMIN, MVT::v8i8, 7}, // pminsb in getMinMaxReductionCost()
4696 {ISD::SMIN, MVT::v16i8, 6}, in getMinMaxReductionCost()
4704 {ISD::SMIN, MVT::v16i16, 6}, in getMinMaxReductionCost()
4706 {ISD::SMIN, MVT::v32i8, 8}, in getMinMaxReductionCost()
4711 {ISD::SMIN, MVT::v32i16, 8}, in getMinMaxReductionCost()
4713 {ISD::SMIN, MVT::v64i8, 10}, in getMinMaxReductionCost()