Home
last modified time | relevance | path

Searched refs:SH (Results 1 – 25 of 86) sorted by relevance

1234

/llvm-project-15.0.7/llvm/test/Analysis/ValueTracking/
H A Dnumsignbits-from-assume.ll9 ; CHECK-NEXT: [[SH:%.*]] = shl nuw nsw i32 [[ADD]], 3
10 ; CHECK-NEXT: ret i32 [[SH]]
24 ; CHECK-NEXT: [[SH:%.*]] = shl nuw nsw i32 [[ADD]], 3
25 ; CHECK-NEXT: ret i32 [[SH]]
39 ; CHECK-NEXT: [[SH:%.*]] = shl nuw nsw i32 [[SUB]], 3
40 ; CHECK-NEXT: ret i32 [[SH]]
54 ; CHECK-NEXT: [[SH:%.*]] = shl nuw nsw i32 [[SUB]], 3
55 ; CHECK-NEXT: ret i32 [[SH]]
70 ; CHECK-NEXT: ret i32 [[SH]]
85 ; CHECK-NEXT: ret i32 [[SH]]
[all …]
/llvm-project-15.0.7/mlir/python/mlir/dialects/linalg/opdsl/ops/
H A Dcore_named_ops.py366 U, I[D.n, D.c, D.oh * S.SH + D.kh * S.DH, D.ow * S.SW +
388 U, I[D.n, D.g, D.c, D.oh * S.SH + D.kh * S.DH, D.ow * S.SW +
393 S.OH * S.SH + S.KH * S.DH, argument
398 S.SH,
523 strides=IndexAttrDef(S.SH,
585 strides=IndexAttrDef(S.SH,
614 S.SH,
644 S.SH,
810 S.OH * S.SH + S.KH * S.DH, argument
837 S.OH * S.SH + S.KH * S.DH, argument
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dxor-ashr.ll82 ; CHECK-NEXT: [[SH:%.*]] = ashr i16 [[ADD:%.*]], 14
83 ; CHECK-NEXT: [[T:%.*]] = trunc i16 [[SH]] to i8
114 ; CHECK-NEXT: [[SH:%.*]] = ashr i16 [[ADD:%.*]], 15
115 ; CHECK-NEXT: [[X:%.*]] = xor i16 [[SH]], 27
116 ; CHECK-NEXT: call void @use16(i16 [[SH]])
127 ; CHECK-NEXT: [[SH:%.*]] = ashr i32 [[ADD:%.*]], 31
128 ; CHECK-NEXT: call void @use32(i32 [[SH]])
142 ; CHECK-NEXT: [[SH:%.*]] = ashr i32 [[ADD:%.*]], 31
143 ; CHECK-NEXT: [[T:%.*]] = trunc i32 [[SH]] to i16
H A Dicmp-topbitssame.ll96 ; CHECK-NEXT: [[SH:%.*]] = lshr i32 [[ADD:%.*]], 8
97 ; CHECK-NEXT: [[CONV_I:%.*]] = trunc i32 [[SH]] to i8
113 ; CHECK-NEXT: [[SH:%.*]] = lshr i16 [[ADD:%.*]], 7
114 ; CHECK-NEXT: [[CONV_I:%.*]] = trunc i16 [[SH]] to i8
130 ; CHECK-NEXT: [[SH:%.*]] = lshr i16 [[ADD:%.*]], 8
131 ; CHECK-NEXT: [[CONV_I:%.*]] = trunc i16 [[SH]] to i8
147 ; CHECK-NEXT: [[SH:%.*]] = lshr i64 [[ADD:%.*]], 32
184 ; CHECK-NEXT: [[SH:%.*]] = lshr i16 [[ADD:%.*]], 8
185 ; CHECK-NEXT: [[CONV_I:%.*]] = trunc i16 [[SH]] to i8
202 ; CHECK-NEXT: [[SH:%.*]] = lshr i16 [[ADD:%.*]], 8
[all …]
H A Dlshr.ll23 ; CHECK-NEXT: ret i32 [[SH]]
34 ; CHECK-NEXT: ret i32 [[SH]]
45 ; CHECK-NEXT: ret i32 [[SH]]
56 ; CHECK-NEXT: ret <2 x i8> [[SH]]
67 ; CHECK-NEXT: ret <2 x i8> [[SH]]
78 ; CHECK-NEXT: ret <2 x i8> [[SH]]
294 ; CHECK-NEXT: ret i18 [[SH]]
307 ; CHECK-NEXT: ret i32 [[SH]]
318 ; CHECK-NEXT: ret <2 x i8> [[SH]]
331 ; CHECK-NEXT: ret <2 x i32> [[SH]]
[all …]
H A Dand2.ll147 ; CHECK-NEXT: [[SH:%.*]] = shl i8 1, [[X:%.*]]
148 ; CHECK-NEXT: [[AND:%.*]] = and i8 [[SH]], 1
149 ; CHECK-NEXT: [[ADD:%.*]] = add i8 [[SH]], [[AND]]
186 ; CHECK-NEXT: [[SH:%.*]] = lshr i8 1, [[X:%.*]]
187 ; CHECK-NEXT: ret i8 [[SH]]
196 ; CHECK-NEXT: [[SH:%.*]] = lshr i8 1, [[X:%.*]]
197 ; CHECK-NEXT: [[ADD:%.*]] = shl nuw nsw i8 [[SH]], 1
210 ; CHECK-NEXT: [[SH:%.*]] = lshr <2 x i8> <i8 1, i8 1>, [[X:%.*]]
211 ; CHECK-NEXT: ret <2 x i8> [[SH]]
H A Dcompare-signs.ll224 ; CHECK-NEXT: [[SH:%.*]] = lshr <2 x i17> [[X:%.*]], <i17 4, i17 4>
225 ; CHECK-NEXT: store <2 x i17> [[SH]], <2 x i17>* [[P1:%.*]], align 8
226 ; CHECK-NEXT: [[TR:%.*]] = trunc <2 x i17> [[SH]] to <2 x i13>
257 ; CHECK-NEXT: [[SH:%.*]] = lshr i32 [[X:%.*]], 24
258 ; CHECK-NEXT: [[TR:%.*]] = trunc i32 [[SH]] to i8
H A Dand-or.ll267 ; CHECK-NEXT: [[SH:%.*]] = lshr i8 [[A:%.*]], 6
269 ; CHECK-NEXT: [[AND:%.*]] = or i8 [[SH]], [[B_MASKED]]
280 ; CHECK-NEXT: [[SH:%.*]] = lshr <2 x i8> [[A:%.*]], <i8 6, i8 6>
282 ; CHECK-NEXT: [[AND:%.*]] = xor <2 x i8> [[SH]], [[B_MASKED]]
294 ; CHECK-NEXT: [[SH:%.*]] = lshr i8 [[A:%.*]], 6
296 ; CHECK-NEXT: [[AND:%.*]] = xor i8 [[C_MASKED]], [[SH]]
309 ; CHECK-NEXT: [[SH:%.*]] = lshr <2 x i8> [[A:%.*]], <i8 6, i8 6>
311 ; CHECK-NEXT: [[AND:%.*]] = or <2 x i8> [[C_MASKED]], [[SH]]
325 ; CHECK-NEXT: [[SH:%.*]] = lshr i8 [[A:%.*]], 6
326 ; CHECK-NEXT: [[OR:%.*]] = or i8 [[SH]], [[B:%.*]]
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCInstPrinter.cpp115 unsigned char SH = MI->getOperand(2).getImm(); in printInst() local
119 if (SH <= 31 && MB == 0 && ME == (31-SH)) { in printInst()
122 if (SH <= 31 && MB == (32-SH) && ME == 31) { in printInst()
124 SH = 32-SH; in printInst()
130 O << ", " << (unsigned int)SH; in printInst()
139 unsigned char SH = MI->getOperand(2).getImm(); in printInst() local
142 if (63-SH == ME) { in printInst()
147 O << ", " << (unsigned int)SH; in printInst()
/llvm-project-15.0.7/clang/include/clang/StaticAnalyzer/Core/BugReporter/
H A DBugReporterVisitors.h244 void addHighPriorityHandler(ExpressionHandlerPtr SH) { in addHighPriorityHandler() argument
245 ExpressionHandlers.push_front(std::move(SH)); in addHighPriorityHandler()
252 void addLowPriorityHandler(ExpressionHandlerPtr SH) { in addLowPriorityHandler() argument
253 ExpressionHandlers.push_back(std::move(SH)); in addLowPriorityHandler()
260 void addHighPriorityHandler(StoreHandlerPtr SH) { in addHighPriorityHandler() argument
261 StoreHandlers.push_front(std::move(SH)); in addHighPriorityHandler()
268 void addLowPriorityHandler(StoreHandlerPtr SH) { in addLowPriorityHandler() argument
269 StoreHandlers.push_back(std::move(SH)); in addLowPriorityHandler()
/llvm-project-15.0.7/llvm/include/llvm/Transforms/Utils/
H A DScalarEvolutionExpander.h272 Value *expandCodeFor(const SCEV *SH, Type *Ty, Instruction *I) {
273 return expandCodeForImpl(SH, Ty, I, true);
280 Value *expandCodeFor(const SCEV *SH, Type *Ty = nullptr) {
281 return expandCodeForImpl(SH, Ty, true);
399 Value *expandCodeForImpl(const SCEV *SH, Type *Ty, bool Root);
405 Value *expandCodeForImpl(const SCEV *SH, Type *Ty, Instruction *I, bool Root);
/llvm-project-15.0.7/libcxx/test/std/strings/string.view/string.view.hash/
H A Dstring_view.pass.cpp42 typedef std::hash<String> SH; in test() typedef
50 SH sh; in test()
/llvm-project-15.0.7/mlir/test/python/dialects/linalg/opdsl/
H A Darguments.py74 strides=IndexAttrDef(S.SH, S.SW, default=[1, 2])):
75 O[D.oh, D.ow] = I[D.oh * S.SH, D.ow * S.SW]
H A Demit_convolution.py19 strides=IndexAttrDef(S.SH, S.SW, default=[1, 1]),
23 U, I[D.n, D.oh * S.SH + D.kh * S.DH, D.ow * S.SW + D.kw * S.DW,
H A Demit_pooling.py21 strides=IndexAttrDef(S.SH, S.SW, default=[1, 1]),
25 cast(U, I[D.n, D.oh * S.SH + D.kh * S.DH, D.ow * S.SW + D.kw * S.DW,
/llvm-project-15.0.7/llvm/test/Transforms/InstSimplify/
H A Dshift-knownbits.ll160 ; CHECK-NEXT: [[SH:%.*]] = lshr i32 [[CT]], 5
161 ; CHECK-NEXT: ret i32 [[SH]]
171 ; CHECK-NEXT: [[SH:%.*]] = lshr i32 [[CT]], 5
172 ; CHECK-NEXT: ret i32 [[SH]]
182 ; CHECK-NEXT: [[SH:%.*]] = lshr <2 x i8> [[CT]], <i8 3, i8 3>
183 ; CHECK-NEXT: ret <2 x i8> [[SH]]
193 ; CHECK-NEXT: [[SH:%.*]] = lshr <2 x i8> [[CT]], <i8 3, i8 0>
194 ; CHECK-NEXT: [[EX:%.*]] = extractelement <2 x i8> [[SH]], i32 0
206 ; CHECK-NEXT: [[SH:%.*]] = lshr <2 x i8> [[CT]], <i8 3, i8 3>
207 ; CHECK-NEXT: ret <2 x i8> [[SH]]
[all …]
H A DAndOrXor.ll84 ; CHECK-NEXT: [[SH:%.*]] = shl i32 2, [[X:%.*]]
85 ; CHECK-NEXT: [[E:%.*]] = zext i32 [[SH]] to i64
761 ; CHECK-NEXT: [[SH:%.*]] = lshr i8 [[X:%.*]], 5
762 ; CHECK-NEXT: ret i8 [[SH]]
772 ; CHECK-NEXT: ret <2 x i8> [[SH]]
781 ; CHECK-NEXT: [[SH:%.*]] = lshr i8 [[X:%.*]], 5
782 ; CHECK-NEXT: [[MASK:%.*]] = and i8 [[SH]], -2
792 ; CHECK-NEXT: [[SH:%.*]] = shl <2 x i8> [[X:%.*]], <i8 6, i8 6>
793 ; CHECK-NEXT: ret <2 x i8> [[SH]]
802 ; CHECK-NEXT: [[SH:%.*]] = shl i8 [[X:%.*]], 6
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dint-sub-07.ll6 ; Check the low end of the SH range.
17 ; Check the high end of the aligned SH range.
29 ; Check the next halfword up, which should use SHY instead of SH.
105 ; Check that SH allows an index.
H A Dint-ssub-02.ll8 ; Check the low end of the SH range.
26 ; Check the high end of the aligned SH range.
45 ; Check the next halfword up, which should use SHY instead of SH.
163 ; Check that SH allows an index.
/llvm-project-15.0.7/llvm/test/Transforms/CodeGenPrepare/X86/
H A Dvec-shift-inseltpoison.ll23 ; AVX2-NEXT: [[SH:%.*]] = lshr <4 x i32> [[Z:%.*]], [[SEL]]
24 ; AVX2-NEXT: ret <4 x i32> [[SH]]
30 ; AVX512BW-NEXT: [[SH:%.*]] = lshr <4 x i32> [[Z:%.*]], [[SEL]]
31 ; AVX512BW-NEXT: ret <4 x i32> [[SH]]
37 ; XOP-NEXT: [[SH:%.*]] = lshr <4 x i32> [[Z:%.*]], [[SEL]]
38 ; XOP-NEXT: ret <4 x i32> [[SH]]
71 ; AVX512BW-NEXT: ret <16 x i16> [[SH]]
77 ; XOP-NEXT: [[SH:%.*]] = lshr <16 x i16> [[Z:%.*]], [[SEL]]
78 ; XOP-NEXT: ret <16 x i16> [[SH]]
119 ; XOP-NEXT: [[SH:%.*]] = lshr <32 x i8> [[Z:%.*]], [[SEL]]
[all …]
H A Dvec-shift.ll23 ; AVX2-NEXT: [[SH:%.*]] = lshr <4 x i32> [[Z:%.*]], [[SEL]]
24 ; AVX2-NEXT: ret <4 x i32> [[SH]]
30 ; AVX512BW-NEXT: [[SH:%.*]] = lshr <4 x i32> [[Z:%.*]], [[SEL]]
31 ; AVX512BW-NEXT: ret <4 x i32> [[SH]]
37 ; XOP-NEXT: [[SH:%.*]] = lshr <4 x i32> [[Z:%.*]], [[SEL]]
38 ; XOP-NEXT: ret <4 x i32> [[SH]]
71 ; AVX512BW-NEXT: ret <16 x i16> [[SH]]
77 ; XOP-NEXT: [[SH:%.*]] = lshr <16 x i16> [[Z:%.*]], [[SEL]]
78 ; XOP-NEXT: ret <16 x i16> [[SH]]
119 ; XOP-NEXT: [[SH:%.*]] = lshr <32 x i8> [[Z:%.*]], [[SEL]]
[all …]
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMScheduleM7.td221 (instregex "t2LDR(B|H|SB|SH)pc")>;
223 (instregex "t2LDR(B|H|SB|SH)T", "t2LDR(B|H|SB|SH)i",
226 (instregex "t2LDR(B|H|SB|SH)s", "tLDR(B|H)r", "tLDR(SB|SH)")>;
228 (instregex "t2LDR(B|H|SB|SH)_(POST|PRE)")>;
386 (instregex "t2(S|SH|U|UH)(ADD16|ADD8|ASX|SAX|SUB16|SUB8)",
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCInstr64Bit.td944 "sradi", "$rA, $rS, $SH", IIC_IntRotateDI,
949 (ins gprc:$rS, u6imm:$SH),
956 "extswsli", "$rA, $rS, $SH", IIC_IntRotateDI,
1056 (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE),
1078 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE),
1085 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE),
1095 "rldicr $rA, $rS, $SH, $MBE", IIC_IntRotateDI,
1099 "rldic", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
1104 (ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1116 (ins g8rc:$rSi, g8rc:$rS, u5imm:$SH, u5imm:$MB,
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dpromote-alloca-vector-to-vector.ll76 ; GCN-DAG: s_mov_b32 s[[SH:[0-9]+]], 0x44004200
78 ; GCN: v_lshrrev_b64 v[{{[0-9:]+}}], v{{[0-9]+}}, s[[[SL]]:[[SH]]]
135 ; GCN-DAG: s_mov_b32 s[[SH:[0-9]+]], 0x40003
137 ; GCN: v_lshrrev_b64 v[{{[0-9:]+}}], v{{[0-9]+}}, s[[[SL]]:[[SH]]]
/llvm-project-15.0.7/mlir/docs/Dialects/Linalg/
H A DOpDSL.md126 strides=IndexAttrDef(S.SH, S.SW, default=[1, 1])):
128 O[D.oh, D.ow] = I[D.oh * S.SH, D.ow * S.SW]
133 the symbols `S.SH` and `S.SW`, which are used to index the input tensor `I`.
140 The `strides` vector elements substitute the symbols `S.SH` and `S.SW` in the
166 strides=IndexAttrDef(S.SH, S.SW, default=[1, 1]),
169 I[D.n, D.oh * S.SH + D.kh * S.DH, D.ow * S.SW + D.kw * S.DW, D.c])

1234