Home
last modified time | relevance | path

Searched refs:SEXTLOAD (Results 1 – 25 of 65) sorted by relevance

123

/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dlegalize-sextload-flat.mir14 ; SI-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
15 ; SI-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
21 ; VI-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
37 ; SI-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
43 ; VI-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
59 ; SI-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
65 ; VI-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
82 ; SI-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
89 ; VI-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
106 ; SI-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
[all …]
H A Dlegalize-sextload-global.mir162 ; GFX8-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
168 ; GFX6-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
185 ; GFX8-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
191 ; GFX6-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
207 ; GFX8-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
213 ; GFX6-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
303 ; GFX8-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
363 ; GFX8-NEXT: $vgpr0 = COPY [[SEXTLOAD]](<2 x s16>)
369 ; GFX6-NEXT: $vgpr0 = COPY [[SEXTLOAD]](<2 x s16>)
386 ; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[SEXTLOAD]](<2 x s32>)
[all …]
H A Dlegalize-sextload-local.mir14 ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p3) :: (load (s8), addrspace 3)
15 ; CHECK-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
30 ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p3) :: (load (s16), addrspace 3)
31 ; CHECK-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
46 ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p3) :: (load (s8), addrspace 3)
47 ; CHECK-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
63 ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p3) :: (load (s8), addrspace 3)
64 ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
80 ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p3) :: (load (s16), addrspace 3)
81 ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
H A Dlegalize-sextload-private.mir15 ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p5) :: (load (s8), addrspace 5)
16 ; CHECK-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
32 ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p5) :: (load (s16), addrspace 5)
33 ; CHECK-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
48 ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p5) :: (load (s8), addrspace 5)
49 ; CHECK-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
65 ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p5) :: (load (s8), addrspace 5)
66 ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
82 ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p5) :: (load (s16), addrspace 5)
83 ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
H A Dpostlegalizer-combiner-sextload-from-sextinreg.mir37 …; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p1) :: (load (s8), align 4, addrsp…
38 ; CHECK-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
97 …; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p1) :: (load (s16), align 4, addrs…
98 ; CHECK-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
116 ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p1) :: (load (s8), addrspace 1)
117 ; CHECK-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
135 …; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p1) :: (volatile load (s8), addrsp…
137 ; CHECK-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
155 ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p1) :: (load (s16), addrspace 1)
156 ; CHECK-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
[all …]
H A Dcombine-sext-inreg.mir15 ; GCN-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p1) :: (load (s8), addrspace 1)
16 ; GCN-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SEXTLOAD]], 7
36 ; GCN-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p1) :: (load (s8), addrspace 1)
37 ; GCN-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
56 ; GCN-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p1) :: (load (s8), addrspace 1)
57 ; GCN-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
77 ; GCN-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SEXTLOAD]], 7
99 ; GCN-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
120 ; GCN-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
307 ; GCN-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[LOAD]], [[SEXTLOAD]]
[all …]
H A Dregbankselect-sextload.mir17 …; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:vgpr(s32) = G_SEXTLOAD [[COPY1]](p4) :: (load (s8), addrspace 4)
35 …; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:vgpr(s32) = G_SEXTLOAD [[COPY1]](p4) :: (load (s8), addrspace 1)
53 …; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:vgpr(s32) = G_SEXTLOAD [[COPY1]](p4) :: (load (s16), addrspace …
71 …; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:vgpr(s32) = G_SEXTLOAD [[COPY1]](p4) :: (load (s16), addrspace …
88 …; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:vgpr(s32) = G_SEXTLOAD [[COPY1]](p3) :: (load (s8), addrspace 3)
106 …; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:vgpr(s32) = G_SEXTLOAD [[COPY1]](p3) :: (load (s16), addrspace …
H A Dlegalize-sextload-constant-32bit.mir77 ; CI-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[MV]](p4) :: (load (s8), addrspace 6)
78 ; CI-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
96 ; CI-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[MV]](p4) :: (load (s16), addrspace 6)
97 ; CI-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
115 …; CI-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[MV]](p4) :: (load (s16), align 1, addrspace …
116 ; CI-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
H A Dregbankselect-widen-scalar-loads.mir428 …; GFX8-NEXT: [[SEXTLOAD:%[0-9]+]]:vgpr(s32) = G_SEXTLOAD [[COPY1]](p1) :: (invariant load (s8), al…
429 ; GFX8-NEXT: S_ENDPGM 0, implicit [[SEXTLOAD]](s32)
435 …; GFX9-NEXT: [[SEXTLOAD:%[0-9]+]]:vgpr(s32) = G_SEXTLOAD [[COPY1]](p1) :: (invariant load (s8), al…
436 ; GFX9-NEXT: S_ENDPGM 0, implicit [[SEXTLOAD]](s32)
443 ; GFX10-NEXT: S_ENDPGM 0, implicit [[SEXTLOAD]](s32)
460 …; GFX8-NEXT: [[SEXTLOAD:%[0-9]+]]:vgpr(s32) = G_SEXTLOAD [[COPY1]](p1) :: (invariant load (s16), a…
461 ; GFX8-NEXT: S_ENDPGM 0, implicit [[SEXTLOAD]](s32)
467 …; GFX9-NEXT: [[SEXTLOAD:%[0-9]+]]:vgpr(s32) = G_SEXTLOAD [[COPY1]](p1) :: (invariant load (s16), a…
468 ; GFX9-NEXT: S_ENDPGM 0, implicit [[SEXTLOAD]](s32)
474 …; GFX10-NEXT: [[SEXTLOAD:%[0-9]+]]:vgpr(s32) = G_SEXTLOAD [[COPY1]](p1) :: (invariant load (s16), …
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dprelegalizercombiner-extending-loads.mir42 ; CHECK: $w0 = COPY [[SEXTLOAD]](s32)
90 ; CHECK: $w0 = COPY [[SEXTLOAD]](s32)
91 ; CHECK: $w1 = COPY [[SEXTLOAD]](s32)
113 ; CHECK: $w1 = COPY [[SEXTLOAD]](s32)
153 ; CHECK: $w1 = COPY [[SEXTLOAD]](s32)
172 ; CHECK: $w1 = COPY [[SEXTLOAD]](s32)
192 ; CHECK: $x1 = COPY [[SEXTLOAD]](s64)
213 ; CHECK: $x1 = COPY [[SEXTLOAD]](s64)
256 ; CHECK: $w0 = COPY [[SEXTLOAD]](s32)
324 ; CHECK: $w1 = COPY [[SEXTLOAD]](s32)
[all …]
H A Dcombine-sext-trunc-sextload.mir14 ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s64) = G_SEXTLOAD [[COPY]](p0) :: (load (s16))
15 ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[SEXTLOAD]](s64)
33 ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s16))
34 ; CHECK: $w0 = COPY [[SEXTLOAD]](s32)
52 ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s16))
53 ; CHECK: $w0 = COPY [[SEXTLOAD]](s32)
H A Dlegalize-extload.mir25 ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s64) = G_SEXTLOAD [[COPY]](p0) :: (load (s32))
26 ; CHECK: $x0 = COPY [[SEXTLOAD]](s64)
42 ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s64) = G_SEXTLOAD [[COPY]](p0) :: (load (s16))
43 ; CHECK: $x0 = COPY [[SEXTLOAD]](s64)
59 ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s64) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
60 ; CHECK: $x0 = COPY [[SEXTLOAD]](s64)
143 ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s64) = G_SEXTLOAD %ptr(p0) :: (load (s8))
144 ; CHECK: $x0 = COPY [[SEXTLOAD]](s64)
H A Dlegalize-sextload.mir10 ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
11 ; CHECK: $w0 = COPY [[SEXTLOAD]](s32)
H A Dprelegalizercombiner-sextload-from-sextinreg.mir16 ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s16) = G_SEXTLOAD [[COPY]](p0) :: (load (s8), align 2)
17 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SEXTLOAD]](s16)
42 ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s16) = G_SEXTLOAD [[COPY]](p0) :: (load (s8), align 2)
44 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SEXTLOAD]](s16)
H A Dcall-lowering-signext.ll58 …; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[FRAME_INDEX1]](p0) :: (invariant load (s8) f…
59 ; CHECK: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[SEXTLOAD]], 1
111 …; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[FRAME_INDEX1]](p0) :: (invariant load (s8) f…
112 ; CHECK: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[SEXTLOAD]], 8
H A Dprelegalizer-combiner-load-and-mask.mir253 ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
254 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SEXTLOAD]], [[C]]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/
H A DzextLoad_and_sextLoad.mir140 ; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
141 ; MIPS32: $v0 = COPY [[SEXTLOAD]](s32)
161 ; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s16) from %ir.px)
162 ; MIPS32: $v0 = COPY [[SEXTLOAD]](s32)
182 ; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s16) = G_SEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
183 ; MIPS32: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SEXTLOAD]](s16)
205 ; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
206 ; MIPS32: $v0 = COPY [[SEXTLOAD]](s32)
227 ; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s64) = G_SEXTLOAD [[COPY]](p0) :: (load (s32) from %ir.px)
228 ; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SEXTLOAD]](s64)
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
H A DzextLoad_and_sextLoad.mir133 ; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
134 ; MIPS32: $v0 = COPY [[SEXTLOAD]](s32)
153 ; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s16) from %ir.px)
154 ; MIPS32: $v0 = COPY [[SEXTLOAD]](s32)
173 ; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
174 ; MIPS32: $v0 = COPY [[SEXTLOAD]](s32)
194 ; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
195 ; MIPS32: $v0 = COPY [[SEXTLOAD]](s32)
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/
H A DzextLoad_and_sextLoad.mir94 ; MIPS32: [[SEXTLOAD:%[0-9]+]]:gprb(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
95 ; MIPS32: $v0 = COPY [[SEXTLOAD]](s32)
115 ; MIPS32: [[SEXTLOAD:%[0-9]+]]:gprb(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s16) from %ir.px)
116 ; MIPS32: $v0 = COPY [[SEXTLOAD]](s32)
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp142 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in BPFTargetLowering()
144 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand); in BPFTargetLowering()
145 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Expand); in BPFTargetLowering()
146 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand); in BPFTargetLowering()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp707 case ISD::SEXTLOAD: OS << ", sext"; break; in print_details()
739 case ISD::SEXTLOAD: OS << ", sext"; break; in print_details()
776 case ISD::SEXTLOAD: OS << ", sext"; break; in print_details()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1404 enum LoadExtType { NON_EXTLOAD = 0, EXTLOAD, SEXTLOAD, ZEXTLOAD }; enumerator
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp49 for (auto Op : {ISD::SEXTLOAD, ISD::ZEXTLOAD, ISD::EXTLOAD}) in R600TargetLowering()
57 setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, MVT::v2i32, in R600TargetLowering()
60 setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, MVT::v4i32, in R600TargetLowering()
1283 if (ExtType == ISD::SEXTLOAD) { // ... ones. in lowerPrivateExtLoad()
1361 if (LoadNode->getExtensionType() == ISD::SEXTLOAD) { in LowerLOAD()
1482 Ext = ISD::SEXTLOAD; in LowerFormalArguments()
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYISelLowering.cpp83 setLoadExtAction(ISD::SEXTLOAD, MVT::i32, MVT::i1, Promote); in CSKYTargetLowering()
94 setLoadExtAction(ISD::SEXTLOAD, MVT::i32, MVT::i8, Expand); in CSKYTargetLowering()
95 setLoadExtAction(ISD::SEXTLOAD, MVT::i32, MVT::i16, Expand); in CSKYTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp66 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in MSP430TargetLowering()
68 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand); in MSP430TargetLowering()
69 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Expand); in MSP430TargetLowering()

123