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Searched refs:SETOLT (Results 1 – 25 of 41) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchFloat32InstrInfo.td157 // SETOGT/SETOGE/SETUGT/SETUGE will expand into SETOLT/SETOLE/SETULT/SETULE.
159 def : PatFPSetcc<SETOLT, FCMP_CLT_S, FPR32>;
184 def : PatFPSelectcc<SETOLT, FCMP_CLT_S, FSEL_S, FPR32>;
H A DLoongArchFloat64InstrInfo.td161 // SETOGT/SETOGE/SETUGT/SETUGE will expand into SETOLT/SETOLE/SETULT/SETULE.
163 def : PatFPSetcc<SETOLT, FCMP_CLT_D, FPR64>;
184 def : PatFPSelectcc<SETOLT, FCMP_CLT_D, FSEL_D, FPR64>;
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1430 SETOLT, // 0 1 0 0 True if ordered and less than enumerator
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYInstrInfoF2.td358 defm : BRCond_Bin_F2<SETOLT, "f2FCMPLT", BT32, MVC32>;
380 def : Pat<(brcond (i32 (setcc FPR32Op:$rs1, fpimm0, SETOLT)), bb:$imm16),
382 def : Pat<(i32 (setcc FPR32Op:$rs1, fpimm0, SETOLT)),
384 def : Pat<(select (i32 (setcc FPR32Op:$rs1, fpimm0, SETOLT)), FPR32Op:$rx, FPR32Op:$false),
H A DCSKYInstrInfoF1.td338 defm : BRCond_Bin<SETOLT, "FCMPLT", BT32, MVC32>;
358 def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETOLT)), bb:$imm16),
360 def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETOLT)),
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DAnalysis.cpp193 case FCmpInst::FCMP_OLT: return ISD::SETOLT; in getFCmpCondCode()
213 case ISD::SETOLT: case ISD::SETULT: return ISD::SETLT; in getFCmpCodeWithoutNaN()
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEISelDAGToDAG.cpp69 case ISD::SETOLT: in fpCondCode2Fcc()
H A DVEInstrInfo.td2089 def : Pat<(f64 (selectcc f64:$LHS, f64:$RHS, f64:$LHS, f64:$RHS, SETOLT)),
2091 def : Pat<(f32 (selectcc f32:$LHS, f32:$RHS, f32:$LHS, f32:$RHS, SETOLT)),
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrFloat.td83 defm LT : ComparisonFP<SETOLT, "lt ", 0x5d, 0x63>;
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoZfh.td317 def : PatSetCC<FPR16, strict_fsetcc, SETOLT, PseudoQuietFLT_H>;
335 def : PatSetCC<FPR16, any_fsetccs, SETOLT, FLT_H>;
H A DRISCVInstrInfoD.td315 def : PatSetCC<FPR64, strict_fsetcc, SETOLT, PseudoQuietFLT_D>;
333 def : PatSetCC<FPR64, any_fsetccs, SETOLT, FLT_D>;
H A DRISCVInstrInfoF.td545 def : PatSetCC<FPR32, strict_fsetcc, SETOLT, PseudoQuietFLT_S>;
563 def : PatSetCC<FPR32, any_fsetccs, SETOLT, FLT_S>;
H A DRISCVInstrInfoVSDPatterns.td961 defm : VPatFPSetCCSDNode_VV_VF_FV<SETOLT, "PseudoVMFLT", "PseudoVMFGT">;
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp449 case ISD::SETOLT: return "setolt"; in getOperationName()
H A DTargetLowering.cpp335 case ISD::SETOLT: in softenSetCCOperands()
4863 case ISD::SETONE: NewCond = IsNegInf ? ISD::SETOGT : ISD::SETOLT; break; in SimplifySetCC()
9777 TLI.isCondCodeLegal(ISD::SETOLT, OpVT))) { in LegalizeSetCCCondCode()
9779 CC2 = ISD::SETOLT; in LegalizeSetCCCondCode()
9788 case ISD::SETOLT: in LegalizeSetCCCondCode()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructions.td329 def COND_OLT : PatFrags<(ops), [(OtherVT SETOLT), (OtherVT SETLT)]>;
H A DSIWholeQuadMode.cpp866 case ISD::SETOLT: in lowerKillF32()
H A DR600ISelLowering.cpp86 setCondCodeAction({ISD::SETO, ISD::SETUO, ISD::SETLT, ISD::SETLE, ISD::SETOLT, in R600TargetLowering()
H A DAMDGPUISelLowering.cpp1327 case ISD::SETOLT: in combineFMinMaxLegacy()
2199 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOLT); in LowerFFLOOR()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp4055 case ISD::SETOLT: in SelectCC()
4082 case ISD::SETOLT: in SelectCC()
4130 case ISD::SETOLT: in getPredicateForSetCC()
4157 case ISD::SETOLT: in getCRIdxForSetCC()
4197 case ISD::SETOLT: CC = ISD::SETOGT; Swap = true; break; in getVCmpInst()
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp859 case ISD::SETOLT: in IntCondCCodeToICC()
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp1558 case ISD::SETOLT: in TranslateM68kCC()
1578 case ISD::SETOLT: // flipped in TranslateM68kCC()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp303 setCondCodeAction(ISD::SETOLT, MVT::v64f16, Expand); in initializeHVXLowering()
316 setCondCodeAction(ISD::SETOLT, MVT::v32f32, Expand); in initializeHVXLowering()
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td745 def SETOLT : CondCode<"FCMP_OLT">;
1352 (setcc node:$lhs, node:$rhs, SETOLT)>;
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp2167 DAG.getConstantFP(0.5, SL, VT), ISD::SETOLT); in LowerFROUND32()
2193 DAG.getConstantFP(0.5, SL, VT), ISD::SETOLT); in LowerFROUND64()

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