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Searched refs:SETOGT (Results 1 – 25 of 37) sorted by relevance

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/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1428 SETOGT, // 0 0 1 0 True if ordered and greater than enumerator
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYInstrInfoF2.td361 defm : BRCond_Bin_SWAP_F2<SETOGT, "f2FCMPLT", BT32, MVC32>;
392 def : Pat<(brcond (i32 (setcc FPR32Op:$rs1, fpimm0, SETOGT)), bb:$imm16),
394 def : Pat<(i32 (setcc FPR32Op:$rs1, fpimm0, SETOGT)),
396 def : Pat<(select (i32 (setcc FPR32Op:$rs1, fpimm0, SETOGT)), FPR32Op:$rx, FPR32Op:$false),
H A DCSKYInstrInfoF1.td341 defm : BRCond_Bin_SWAP<SETOGT, "FCMPLT", BT32, MVC32>;
366 def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETOGT)), bb:$imm16),
368 def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETOGT)),
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DAnalysis.cpp191 case FCmpInst::FCMP_OGT: return ISD::SETOGT; in getFCmpCondCode()
215 case ISD::SETOGT: case ISD::SETUGT: return ISD::SETGT; in getFCmpCodeWithoutNaN()
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEISelDAGToDAG.cpp72 case ISD::SETOGT: in fpCondCode2Fcc()
H A DVEInstrInfo.td2072 def : Pat<(f64 (selectcc f64:$LHS, f64:$RHS, f64:$LHS, f64:$RHS, SETOGT)),
2074 def : Pat<(f32 (selectcc f32:$LHS, f32:$RHS, f32:$LHS, f32:$RHS, SETOGT)),
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrFloat.td85 defm GT : ComparisonFP<SETOGT, "gt ", 0x5e, 0x64>;
H A DWebAssemblyInstrSIMD.td724 defm GT : SIMDConditionFP<"gt", SETOGT, 68>;
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchFloat32InstrInfo.td157 // SETOGT/SETOGE/SETUGT/SETUGE will expand into SETOLT/SETOLE/SETULT/SETULE.
H A DLoongArchFloat64InstrInfo.td161 // SETOGT/SETOGE/SETUGT/SETUGE will expand into SETOLT/SETOLE/SETULT/SETULE.
H A DLoongArchISelLowering.cpp68 static const ISD::CondCode FPCCToExpand[] = {ISD::SETOGT, ISD::SETOGE, in LoongArchTargetLowering()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp447 case ISD::SETOGT: return "setogt"; in getOperationName()
H A DTargetLowering.cpp347 case ISD::SETOGT: in softenSetCCOperands()
4863 case ISD::SETONE: NewCond = IsNegInf ? ISD::SETOGT : ISD::SETOLT; break; in SimplifySetCC()
9618 ISD::CondCode::SETOGT); in expandFP_TO_INT_SAT()
9776 (TLI.isCondCodeLegal(ISD::SETOGT, OpVT) || in LegalizeSetCCCondCode()
9778 CC1 = ISD::SETOGT; in LegalizeSetCCCondCode()
9786 case ISD::SETOGT: in LegalizeSetCCCondCode()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp4063 case ISD::SETOGT: in SelectCC()
4090 case ISD::SETOGT: in SelectCC()
4136 case ISD::SETOGT: in getPredicateForSetCC()
4159 case ISD::SETOGT: in getCRIdxForSetCC()
4197 case ISD::SETOLT: CC = ISD::SETOGT; Swap = true; break; in getVCmpInst()
4206 case ISD::SETULE: CC = ISD::SETOGT; Negate = true; break; in getVCmpInst()
4220 case ISD::SETOGT: in getVCmpInst()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructions.td327 def COND_OGT : PatFrags<(ops), [(OtherVT SETOGT), (OtherVT SETGT)]>;
H A DSIWholeQuadMode.cpp858 case ISD::SETOGT: in lowerKillF32()
H A DAMDGPUISelLowering.cpp1354 case ISD::SETOGT: { in combineFMinMaxLegacy()
2045 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOGT); in LowerFCEIL()
2137 SDValue Cond = DAG.getSetCC(SL, SetCCVT, Fabs, C2, ISD::SETOGT); in LowerFRINT()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp257 setCondCodeAction(ISD::SETOGT, MVT::f32, Expand); in MipsSETargetLowering()
262 setCondCodeAction(ISD::SETOGT, MVT::f64, Expand); in MipsSETargetLowering()
394 setCondCodeAction(ISD::SETOGT, Ty, Expand); in addMSAFloatType()
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp860 case ISD::SETOGT: in IntCondCCodeToICC()
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td743 def SETOGT : CondCode<"FCMP_OGT">;
1348 (setcc node:$lhs, node:$rhs, SETOGT)>;
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp2923 case ISD::SETOGT: in getVectorComparison()
3043 SDValue LT = getVectorCmp(DAG, getVectorComparison(ISD::SETOGT, Mode), in lowerVectorSETCC()
3060 SDValue LT = getVectorCmp(DAG, getVectorComparison(ISD::SETOGT, Mode), in lowerVectorSETCC()
3062 SDValue GT = getVectorCmp(DAG, getVectorComparison(ISD::SETOGT, Mode), in lowerVectorSETCC()
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp2162 ISD::SETOGT); in LowerFROUND32()
2205 ISD::SETOGT); in LowerFROUND64()
H A DNVPTXISelDAGToDAG.cpp545 case ISD::SETOGT: in getPTXCmpMode()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SVEInstrInfo.td1795 defm FCMGT_PPzZZ : sve_fp_3op_p_pd_cc<0b001, "fcmgt", SETOGT, SETGT, SETOLT, SETLT>;
1803 defm FCMGT_PPzZ0 : sve_fp_2op_p_pd<0b001, "fcmgt", SETOGT, SETGT, SETOLT, SETLT>;
1804 defm FCMLT_PPzZ0 : sve_fp_2op_p_pd<0b010, "fcmlt", SETOLT, SETLT, SETOGT, SETGT>;
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp1579 case ISD::SETOGT: in TranslateM68kCC()

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