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Searched refs:SELECT_CC (Results 1 – 25 of 59) sorted by relevance

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/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dpr45709.ll6 ; There is code in the SDAG to expand FMAX/FMIN with fast flags to SELECT_CC.
7 ; On PPC, we had SELECT_CC legalized using Promote for all vector types
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A D2010-04-09-NeonSelect.ll2 ; rdar://7770501 : Don't crash on SELECT and SELECT_CC with NEON vector values.
/llvm-project-15.0.7/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.td356 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
359 def SELECT_CC : PseudoInstXCore<(outs GRRegs:$dst),
361 "# SELECT_CC PSEUDO!",
1202 (SELECT_CC GRRegs:$lhs, GRRegs:$T, GRRegs:$F)>;
1205 (SELECT_CC GRRegs:$lhs, GRRegs:$F, GRRegs:$T)>;
1208 (SELECT_CC (LSS_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>;
1210 (SELECT_CC (LSU_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>;
1212 (SELECT_CC (LSS_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
1216 (SELECT_CC (EQ_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
1300 (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$T, GRRegs:$F)>;
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp106 setOperationAction(ISD::SELECT_CC, {MVT::f32, MVT::i32}, Custom); in R600TargetLowering()
200 ISD::SELECT_CC, ISD::INSERT_VECTOR_ELT, ISD::LOAD}); in R600TargetLowering()
408 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); in LowerOperation()
851 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC); in LowerSELECT_CC()
908 SDValue SelectNode = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, in LowerSELECT_CC()
932 SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, LHS, RHS, HWTrue, HWFalse, CC); in LowerSELECT_CC()
934 return DAG.getNode(ISD::SELECT_CC, DL, VT, in LowerSELECT_CC()
1727 if (SelectCC.getOpcode() != ISD::SELECT_CC || in PerformDAGCombine()
1735 return DAG.getNode(ISD::SELECT_CC, DL, N->getValueType(0), in PerformDAGCombine()
1818 case ISD::SELECT_CC: { in PerformDAGCombine()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFISelLowering.h28 SELECT_CC, enumerator
H A DBPFISelLowering.cpp119 setOperationAction(ISD::SELECT_CC, VT, Custom); in BPFTargetLowering()
288 case ISD::SELECT_CC: in LowerOperation()
622 return DAG.getNode(BPFISD::SELECT_CC, DL, VTs, Ops); in LowerSELECT_CC()
633 case BPFISD::SELECT_CC: in getTargetNodeName()
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.h38 SELECT_CC, enumerator
H A DLanaiISelLowering.cpp90 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in LanaiTargetLowering()
186 case ISD::SELECT_CC: in LowerOperation()
1003 return DAG.getNode(LanaiISD::SELECT_CC, DL, VTs, TrueV, FalseV, TargetCC, in LowerSELECT_CC()
1107 case LanaiISD::SELECT_CC: in getTargetNodeName()
1503 case LanaiISD::SELECT_CC: in computeKnownBitsForTargetNode()
/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.h64 SELECT_CC, enumerator
H A DMSP430ISelLowering.cpp96 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom); in MSP430TargetLowering()
97 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom); in MSP430TargetLowering()
349 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); in LowerOperation()
1214 return DAG.getNode(MSP430ISD::SELECT_CC, dl, Op.getValueType(), Ops); in LowerSETCC()
1232 return DAG.getNode(MSP430ISD::SELECT_CC, dl, Op.getValueType(), Ops); in LowerSELECT_CC()
1385 case MSP430ISD::SELECT_CC: return "MSP430ISD::SELECT_CC"; in getTargetNodeName()
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRISelLowering.h72 SELECT_CC enumerator
H A DAVRISelLowering.cpp104 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom); in AVRTargetLowering()
105 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom); in AVRTargetLowering()
106 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); in AVRTargetLowering()
107 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); in AVRTargetLowering()
261 NODE(SELECT_CC); in getTargetNodeName()
804 return DAG.getNode(AVRISD::SELECT_CC, dl, VTs, Ops); in LowerSELECT_CC()
821 return DAG.getNode(AVRISD::SELECT_CC, DL, VTs, Ops); in LowerSETCC()
855 case ISD::SELECT_CC: in LowerOperation()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeFloatTypes.cpp133 case ISD::SELECT_CC: R = SoftenFloatRes_SELECT_CC(N); break; in SoftenFloatResult()
739 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), in SoftenFloatRes_SELECT_CC()
855 case ISD::SELECT_CC: Res = SoftenFloatOp_SELECT_CC(N); break; in SoftenFloatOperand()
1205 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; in ExpandFloatResult()
1805 case ISD::SELECT_CC: Res = ExpandFloatOp_SELECT_CC(N); break; in ExpandFloatOperand()
2118 case ISD::SELECT_CC: R = PromoteFloatOp_SELECT_CC(N, OpNo); break; in PromoteFloatOperand()
2186 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), N->getValueType(0), in PromoteFloatOp_SELECT_CC()
2296 case ISD::SELECT_CC: R = PromoteFloatRes_SELECT_CC(N); break; in PromoteFloatResult()
2520 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), in PromoteFloatRes_SELECT_CC()
2660 case ISD::SELECT_CC: R = SoftPromoteHalfRes_SELECT_CC(N); break; in SoftPromoteHalfResult()
[all …]
H A DLegalizeTypesGeneric.cpp564 Lo = DAG.getNode(ISD::SELECT_CC, dl, LL.getValueType(), N->getOperand(0), in SplitRes_SELECT_CC()
566 Hi = DAG.getNode(ISD::SELECT_CC, dl, LH.getValueType(), N->getOperand(0), in SplitRes_SELECT_CC()
H A DLegalizeDAG.cpp1034 case ISD::SELECT_CC: in LegalizeOp()
1041 unsigned CCOperand = Opc == ISD::SELECT_CC ? 4 in LegalizeOp()
1055 if (Node->getOpcode() == ISD::SELECT_CC) in LegalizeOp()
3681 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2, in ExpandNode()
3688 case ISD::SELECT_CC: { in ExpandNode()
3751 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), in ExpandNode()
3756 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, in ExpandNode()
4463 Node->getOpcode() == ISD::SELECT_CC) in PromoteNode()
4667 case ISD::SELECT_CC: { in PromoteNode()
4691 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, NVT, {Tmp1, Tmp2, Tmp3, Tmp4, Cond}, in PromoteNode()
H A DLegalizeVectorOps.cpp351 case ISD::SELECT_CC: in LegalizeOp()
740 case ISD::SELECT_CC: { in Expand()
1500 DAG.getNode(ISD::SELECT_CC, dl, VT, LHS, RHS, in ExpandSETCC()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h728 SELECT_CC, enumerator
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp73 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); in LoongArchTargetLowering()
77 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); in LoongArchTargetLowering()
83 setOperationAction(ISD::SELECT_CC, GRLenVT, Expand); in LoongArchTargetLowering()
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/
H A Drvv-vscale.i64.ll112 ; but not until after the select becomes RISCVISD::SELECT_CC. Make sure we
/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp145 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in ARCTargetLowering()
793 case ISD::SELECT_CC: in LowerOperation()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h39 SELECT_CC, enumerator
H A DRISCVISelLowering.cpp189 setOperationAction(ISD::SELECT_CC, XLenVT, Expand); in RISCVTargetLowering()
607 setOperationAction(ISD::SELECT_CC, VT, Expand); in RISCVTargetLowering()
698 setOperationAction(ISD::SELECT_CC, VT, Expand); in RISCVTargetLowering()
841 setOperationAction(ISD::SELECT_CC, VT, Expand); in RISCVTargetLowering()
910 setOperationAction(ISD::SELECT_CC, VT, Expand); in RISCVTargetLowering()
7965 Slct.getOpcode() != RISCVISD::SELECT_CC) || in combineSelectAndUse()
7994 if (Slct.getOpcode() == RISCVISD::SELECT_CC) in combineSelectAndUse()
9059 case RISCVISD::SELECT_CC: { in PerformDAGCombine()
9558 case RISCVISD::SELECT_CC: { in computeKnownBitsForTargetNode()
9657 case RISCVISD::SELECT_CC: { in ComputeNumSignBitsForTargetNode()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp491 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in PPCTargetLowering()
492 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); in PPCTargetLowering()
819 setOperationAction(ISD::SELECT_CC, VT, Promote); in PPCTargetLowering()
820 AddPromotedToType (ISD::SELECT_CC, VT, MVT::v4i32); in PPCTargetLowering()
13434 N->getOpcode() == ISD::SELECT_CC) { in DAGCombineTruncBoolExt()
13650 case ISD::SELECT_CC: C = 2; break; in DAGCombineTruncBoolExt()
13717 N->getOperand(0).getOpcode() != ISD::SELECT_CC) in DAGCombineExtBoolTrunc()
13877 case ISD::SELECT_CC: C = 2; break; in DAGCombineExtBoolTrunc()
13895 PromOp.getOpcode() == ISD::SELECT_CC) { in DAGCombineExtBoolTrunc()
13926 PromOp.getOpcode() == ISD::SELECT_CC) { in DAGCombineExtBoolTrunc()
[all …]
H A DPPCISelDAGToDAG.cpp3845 Compare.getOpcode() == ISD::SELECT_CC) && in getSETCCInGPR()
3857 int CCOpNum = Compare.getOpcode() == ISD::SELECT_CC ? 4 : 2; in getSETCCInGPR()
4509 assert(N->getOpcode() == ISD::SELECT_CC && "Expecting a SELECT_CC here."); in mayUseP9Setb()
4530 (FalseRes.getOpcode() != ISD::SELECT_CC || CC != ISD::SETEQ))) in mayUseP9Setb()
4533 SDValue SetOrSelCC = FalseRes.getOpcode() == ISD::SELECT_CC in mayUseP9Setb()
4536 bool InnerIsSel = SetOrSelCC.getOpcode() == ISD::SELECT_CC; in mayUseP9Setb()
4538 SetOrSelCC.getOpcode() != ISD::SELECT_CC) in mayUseP9Setb()
5539 case ISD::SELECT_CC: { in Select()
6088 if (O.getOpcode() != ISD::SELECT_CC) in combineToCMPB()
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1650 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in SparcTargetLowering()
1651 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in SparcTargetLowering()
1652 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); in SparcTargetLowering()
1653 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom); in SparcTargetLowering()
1670 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); in SparcTargetLowering()
3149 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, *this, in LowerOperation()

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