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Searched refs:Rt2 (Results 1 – 18 of 18) sorted by relevance

/llvm-project-15.0.7/llvm/test/MC/AArch64/
H A Darm64-diags.s156 ; where Rt==Rn or Rt2==Rn are unpredicatable.
194 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
197 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
200 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
203 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
206 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
209 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
212 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
215 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
218 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
[all …]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/AArch64/
H A Dbasic-a64-unpredictable.txt46 # Unpredictable if Rt == Rt2 on a load.
67 # Unpredictable if Rt == Rt2 on a load.
/llvm-project-15.0.7/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp1249 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); in DecodeExclusiveLdStInstruction() local
1303 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); in DecodeExclusiveLdStInstruction()
1312 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); in DecodeExclusiveLdStInstruction()
1321 Rt == Rt2) in DecodeExclusiveLdStInstruction()
1332 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); in DecodePairLdStInstruction() local
1396 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); in DecodePairLdStInstruction()
1409 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); in DecodePairLdStInstruction()
1420 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder); in DecodePairLdStInstruction()
1431 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder); in DecodePairLdStInstruction()
1442 DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder); in DecodePairLdStInstruction()
[all …]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/
H A Dinvalid-thumbv7-xfail.txt9 # Rt == Rt2 is UNPREDICTABLE
/llvm-project-15.0.7/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp2217 unsigned Rt2 = Rt + 1; in DecodeAddrMode3Instruction() local
2245 if (Rt2 == 15) in DecodeAddrMode3Instruction()
2264 if (Rt2 == 15) in DecodeAddrMode3Instruction()
2270 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) in DecodeAddrMode3Instruction()
5802 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) in DecodeVMOVSRR()
5828 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) in DecodeVMOVRRS()
5890 if (writeback && (Rn == Rt || Rn == Rt2)) in DecodeT2LDRDPreInstruction()
5892 if (Rt == Rt2) in DecodeT2LDRDPreInstruction()
5927 if (writeback && (Rn == Rt || Rn == Rt2)) in DecodeT2STRDPreInstruction()
5995 if (Rt == Rn || Rn == Rt2) in DecodeSwap()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMInstrVFP.td1213 bits<4> Rt2;
1219 let Inst{19-16} = Rt2;
1229 // $Rt2 = EXTRACT_SUBREG $Dm, ssub_1
1241 bits<4> Rt2;
1247 let Inst{19-16} = Rt2;
1262 (outs DPR:$Dm), (ins GPR:$Rt, GPR:$Rt2),
1270 bits<4> Rt2;
1276 let Inst{19-16} = Rt2;
1285 // $Dm = REG_SEQUENCE $Rt, ssub_0, $Rt2, ssub_1
2760 def : VFP2InstAlias<"vmov${p}.f64 $Rt, $Rt2, $Dn",
[all …]
H A DARMInstrThumb2.td1456 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
3640 bits<4> Rt2;
3641 let Inst{11-8} = Rt2;
3674 bits<4> Rt2;
3675 let Inst{11-8} = Rt2;
3721 bits<4> Rt2;
3722 let Inst{11-8} = Rt2;
3767 bits<4> Rt2;
3768 let Inst{11-8} = Rt2;
4557 bits<4> Rt2;
[all …]
H A DARMInstrInfo.td2966 "ldrd", "\t$Rt, $Rt2, $addr!",
2979 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
3299 "strd", "\t$Rt, $Rt2, $addr!",
5686 bits<4> Rt2;
5692 let Inst{19-16} = Rt2;
5700 GPRnopc:$Rt2, c_imm:$CRm),
5704 (outs GPRnopc:$Rt, GPRnopc:$Rt2),
5717 bits<4> Rt2;
5723 let Inst{19-16} = Rt2;
5733 GPRnopc:$Rt2, c_imm:$CRm),
[all …]
H A DARMInstrFormats.td715 : AI<oops, iops, MiscFrm, NoItinerary, opc, "\t$Rt, $Rt2, $addr", pattern> {
717 bits<4> Rt2;
725 let Inst{3-0} = Rt2;
1414 bits<4> Rt2;
1424 let Inst{11-8} = Rt2{3-0};
1433 bits<4> Rt2;
1444 let Inst{11-8} = Rt2{3-0};
H A DARMInstrMVE.td5877 bits<5> Rt2;
5886 let Inst{19-16} = Rt2{3-0};
5924 (ins MQPR:$QdSrc, rGPR:$Rt, rGPR:$Rt2),
5925 0b1, "$Qd$idx, $QdSrc$idx2, $Rt, $Rt2",
5930 def MVE_VMOV_rr_q : MVE_VMOV_64bit<(outs rGPR:$Rt, rGPR:$Rt2), (ins MQPR:$Qd),
5931 0b0, "$Rt, $Rt2, $Qd$idx, $Qd$idx2", ""> {
/llvm-project-15.0.7/lldb/source/Plugins/Instruction/ARM64/
H A DEmulateInstructionARM64.cpp698 uint32_t Rt2 = Bits32(opcode, 14, 10); in EmulateLDPSTP() local
704 integer t2 = UInt(Rt2); in EmulateLDPSTP()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64InstrFormats.td4170 bits<5> Rt2;
4179 let Inst{14-10} = Rt2;
4219 bits<5> Rt2;
4228 let Inst{14-10} = Rt2;
4260 bits<5> Rt2;
4269 let Inst{14-10} = Rt2;
4301 bits<5> Rt2;
4310 let Inst{14-10} = Rt2;
4416 bits<5> Rt2;
4418 let Inst{14-10} = Rt2;
[all …]
H A DAArch64InstrInfo.td2022 def : Pat<(int_aarch64_stgp (am_indexed7s128 GPR64sp:$Rn, simm7s16:$imm), GPR64:$Rt, GPR64:$Rt2),
2023 (STGPi $Rt, $Rt2, $Rn, $imm)>;
3287 def : Pat<(AArch64stp GPR64z:$Rt, GPR64z:$Rt2, (am_indexed7s64 GPR64sp:$Rn, simm7s8:$offset)),
3288 (STPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, simm7s8:$offset)>;
3290 def : Pat<(AArch64stnp FPR128:$Rt, FPR128:$Rt2, (am_indexed7s128 GPR64sp:$Rn, simm7s16:$offset)),
3291 (STNPQi FPR128:$Rt, FPR128:$Rt2, GPR64sp:$Rn, simm7s16:$offset)>;
/llvm-project-15.0.7/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp4740 unsigned Rt2 = Inst.getOperand(2).getReg(); in validateInstruction() local
4745 if (RI->isSubRegisterEq(Rn, Rt2)) in validateInstruction()
4757 unsigned Rt2 = Inst.getOperand(1).getReg(); in validateInstruction() local
4758 if (Rt == Rt2) in validateInstruction()
4770 unsigned Rt2 = Inst.getOperand(2).getReg(); in validateInstruction() local
4771 if (Rt == Rt2) in validateInstruction()
4786 unsigned Rt2 = Inst.getOperand(2).getReg(); in validateInstruction() local
4791 if (RI->isSubRegisterEq(Rn, Rt2)) in validateInstruction()
4867 unsigned Rt2 = Inst.getOperand(2).getReg(); in validateInstruction() local
4869 if (RI->isSubRegisterEq(Rt1, Rs) || RI->isSubRegisterEq(Rt2, Rs) || in validateInstruction()
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Ddiagnostics.s328 @ Out of order Rt/Rt2 operands for ldrexd/strexd
402 @ Out of order Rt/Rt2 operands for ldrd/strd
/llvm-project-15.0.7/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp7453 unsigned Rt2 = MRI->getEncodingValue(Reg2); in ParseInstruction() local
7456 if (Rt + 1 != Rt2 || (Rt & 1)) { in ParseInstruction()
7574 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(RtIndex + 1).getReg()); in validateLDRDSTRD() local
7588 if (Rt2 != Rt + 1) { in validateLDRDSTRD()
7602 if (Rt2 == Rt) in validateLDRDSTRD()
7610 if (Rn == Rt || Rn == Rt2) { in validateLDRDSTRD()
/llvm-project-15.0.7/lldb/source/Plugins/Instruction/ARM/
H A DEmulateInstructionARM.cpp11189 uint32_t Rt2 = ReadCoreReg(t2, &success); in EmulateSTRDReg() local
11198 if (!MemAWrite(context, address + 4, Rt2, addr_byte_size)) in EmulateSTRDReg()
/llvm-project-15.0.7/clang/lib/CodeGen/
H A DCGBuiltin.cpp7560 Value *Rt2 = Builder.CreateLShr(RtAndRt2, C1); in EmitARMBuiltinExpr() local
7561 Rt2 = Builder.CreateTruncOrBitCast(Rt2, Int32Ty); in EmitARMBuiltinExpr()
7563 return Builder.CreateCall(F, {Coproc, Opc1, Rt, Rt2, CRm}); in EmitARMBuiltinExpr()