Lines Matching refs:Rt2
1456 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1458 IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", "",
1459 [(set rGPR:$Rt, rGPR:$Rt2, (ARMldrd t2addrmode_imm8s4:$addr))]>,
1647 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4:$addr),
1648 IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", "",
1649 [(ARMstrd rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4:$addr)]>,
1775 def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1777 "ldrd", "\t$Rt, $Rt2, $addr!", "$addr.base = $wb", []>,
1783 def t2LDRD_POST : T2Ii8s4post<0, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1785 IIC_iLoad_d_ru, "ldrd", "\t$Rt, $Rt2, $addr$imm",
1790 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4_pre:$addr),
1791 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr!",
1798 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr,
1800 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr$imm",
3634 def t2LDREXD : T2I_ldrex<0b0111, (outs rGPR:$Rt, rGPR:$Rt2),
3637 "ldrexd", "\t$Rt, $Rt2, $addr", "",
3640 bits<4> Rt2;
3641 let Inst{11-8} = Rt2;
3668 def t2LDAEXD : T2I_ldrex<0b1111, (outs rGPR:$Rt, rGPR:$Rt2),
3671 "ldaexd", "\t$Rt, $Rt2, $addr", "",
3674 bits<4> Rt2;
3675 let Inst{11-8} = Rt2;
3716 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr),
3718 "strexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
3721 bits<4> Rt2;
3722 let Inst{11-8} = Rt2;
3762 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr),
3764 "stlexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
3767 bits<4> Rt2;
3768 let Inst{11-8} = Rt2;
4551 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4557 bits<4> Rt2;
4563 let Inst{19-16} = Rt2;
4619 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2,
4621 [(int_arm_mcrr timm:$cop, timm:$opc1, GPR:$Rt, GPR:$Rt2,
4624 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2,
4627 GPR:$Rt2, timm:$CRm)]> {
4632 def t2MRRC : t2MovRRCopro<0b1110, "mrrc", 1, (outs GPR:$Rt, GPR:$Rt2),
4635 def t2MRRC2 : t2MovRRCopro<0b1111, "mrrc2", 1, (outs GPR:$Rt, GPR:$Rt2),