Searched refs:RetReg (Results 1 – 7 of 7) sorted by relevance
| /llvm-project-15.0.7/clang/unittests/StaticAnalyzer/ |
| H A D | TestReturnValueUnderConstruction.cpp | 39 const auto *RetReg = cast<TypedValueRegion>(RetVal->getAsRegion()); in checkPostCall() local
41 ASSERT_EQ(OrigExpr->getType(), RetReg->getValueType()); in checkPostCall()
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| /llvm-project-15.0.7/clang/lib/StaticAnalyzer/Checkers/ |
| H A D | DynamicTypePropagation.cpp | 309 const MemRegion *RetReg = Call.getReturnValue().getAsRegion(); in checkPostCall() local
310 if (!RetReg) in checkPostCall()
342 C.addTransition(setDynamicTypeInfo(State, RetReg, DynResTy, false)); in checkPostCall()
352 C.addTransition(setDynamicTypeInfo(State, RetReg, RecDynType)); in checkPostCall()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 1724 Register RetReg = VA.getLocReg(); in SelectRet() local
1733 TII.get(TargetOpcode::COPY), RetReg).addReg(SrcReg); in SelectRet()
1735 RetRegs.push_back(RetReg); in SelectRet()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86FastISel.cpp | 1289 unsigned RetReg = Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX; in X86SelectRet() local
1291 TII.get(TargetOpcode::COPY), RetReg).addReg(Reg); in X86SelectRet()
1292 RetRegs.push_back(RetReg); in X86SelectRet()
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| /llvm-project-15.0.7/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 2786 Register RetReg = MF.addLiveIn(SP::I7, TLI.getRegClassFor(PtrVT)); in LowerRETURNADDR() local
2787 RetAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, RetReg, VT); in LowerRETURNADDR()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 3862 for (unsigned RetReg : RetRegs) in selectRet() local
3863 MIB.addReg(RetReg, RegState::Implicit); in selectRet()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsInstrInfo.td | 1581 Register RetReg, RegisterOperand ResRO = RO>:
1583 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)> {
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