Searched refs:ResRegs (Results 1 – 4 of 4) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | InlineAsmLowering.cpp | 602 ArrayRef<Register> ResRegs = GetOrCreateVRegs(Call); in lowerInlineAsm() local
603 if (ResRegs.size() != OutputOperands.size()) { in lowerInlineAsm()
608 for (unsigned int i = 0, e = ResRegs.size(); i < e; i++) { in lowerInlineAsm()
625 LLT ResTy = MRI->getType(ResRegs[i]); in lowerInlineAsm()
633 MIRBuilder.buildTrunc(ResRegs[i], Tmp1Reg); in lowerInlineAsm()
635 MIRBuilder.buildCopy(ResRegs[i], SrcReg); in lowerInlineAsm()
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| H A D | CallLowering.cpp | 82 ArrayRef<Register> ResRegs, in lowerCall() argument
144 Info.OrigRet = ArgInfo{ResRegs, RetTy, 0, ISD::ArgFlagsTy{}}; in lowerCall()
151 ReturnHintAlignReg = MRI.cloneVirtualRegister(ResRegs[0]); in lowerCall()
169 MIRBuilder.buildAssertAlign(ResRegs[0], ReturnHintAlignReg, in lowerCall()
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| H A D | IRTranslator.cpp | 1436 ArrayRef<Register> ResRegs = getOrCreateVRegs(U); in translateSelect() local
1444 for (unsigned i = 0; i < ResRegs.size(); ++i) { in translateSelect()
1445 MIRBuilder.buildSelect(ResRegs[i], Tst, Op0Regs[i], Op1Regs[i], Flags); in translateSelect()
1697 ArrayRef<Register> ResRegs = getOrCreateVRegs(CI); in translateOverflowIntrinsic() local
1699 Op, {ResRegs[0], ResRegs[1]}, in translateOverflowIntrinsic()
2678 ArrayRef<Register> ResRegs = getOrCreateVRegs(LP); in translateLandingPad() local
2679 MIRBuilder.buildCopy(ResRegs[0], ExceptionReg); in translateLandingPad()
2688 MIRBuilder.buildCast(ResRegs[1], PtrVReg); in translateLandingPad()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | CallLowering.h | 577 ArrayRef<Register> ResRegs,
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