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/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600RegisterInfo.td174 def R600_LDS_SRC_REG : RegisterClass<"AMDGPU", [i32], 32,
177 def R600_KC0_X : RegisterClass <"AMDGPU", [f32, i32], 32,
180 def R600_KC0_Y : RegisterClass <"AMDGPU", [f32, i32], 32,
183 def R600_KC0_Z : RegisterClass <"AMDGPU", [f32, i32], 32,
186 def R600_KC0_W : RegisterClass <"AMDGPU", [f32, i32], 32,
189 def R600_KC0 : RegisterClass <"AMDGPU", [f32, i32], 32,
193 def R600_KC1_X : RegisterClass <"AMDGPU", [f32, i32], 32,
196 def R600_KC1_Y : RegisterClass <"AMDGPU", [f32, i32], 32,
199 def R600_KC1_Z : RegisterClass <"AMDGPU", [f32, i32], 32,
202 def R600_KC1_W : RegisterClass <"AMDGPU", [f32, i32], 32,
[all …]
H A DMIMGInstructions.td369 RegisterClass DataRC, RegisterClass AddrRC,
394 RegisterClass DataRC, RegisterClass AddrRC,
511 RegisterClass data_rc,
512 RegisterClass addr_rc,
538 RegisterClass DataRC, RegisterClass AddrRC,
564 RegisterClass DataRC, RegisterClass AddrRC,
718 RegisterClass DataRC, RegisterClass AddrRC,
748 RegisterClass DataRC, RegisterClass AddrRC,
896 RegisterClass DataRC, RegisterClass AddrRC,
923 RegisterClass DataRC, RegisterClass AddrRC,
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/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86RegisterInfo.td396 def GR8 : RegisterClass<"X86", [i8], 8,
406 def GRH8 : RegisterClass<"X86", [i8], 8,
410 def GR16 : RegisterClass<"X86", [i16], 16,
415 def GRH16 : RegisterClass<"X86", [i16], 16,
420 def GR32 : RegisterClass<"X86", [i32], 32,
429 def GR64 : RegisterClass<"X86", [i64], 64,
469 def GR8_NOREX : RegisterClass<"X86", [i8], 8,
477 def GR16_NOREX : RegisterClass<"X86", [i16], 16,
480 def GR32_NOREX : RegisterClass<"X86", [i32], 32,
483 def GR64_NOREX : RegisterClass<"X86", [i64], 64,
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/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/RISCV/
H A Dreg-usage.ll26 ; CHECK-SCALAR-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 2 registers
27 ; CHECK-SCALAR-NEXT: LV(REG): RegisterClass: RISCV::FPRRC, 2 registers
29 ; CHECK-SCALAR-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 1 registers
31 ; CHECK-LMUL1-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 2 registers
32 ; CHECK-LMUL1-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 2 registers
34 ; CHECK-LMUL1-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 2 registers
36 ; CHECK-LMUL2-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 2 registers
37 ; CHECK-LMUL2-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 4 registers
39 ; CHECK-LMUL2-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 4 registers
42 ; CHECK-LMUL4-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 8 registers
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsRegisterInfo.td282 RegisterClass<"Mips", regTypes, 32, (add
298 def GPR32ZERO : RegisterClass<"Mips", [i32], 32, (add
318 def GPRMM16 : RegisterClass<"Mips", [i32], 32, (add
324 def GPRMM16Zero : RegisterClass<"Mips", [i32], 32, (add
352 def GPR64 : RegisterClass<"Mips", [i64], 64, (add
366 def CPU16Regs : RegisterClass<"Mips", [i32], 32, (add
399 def AFGR64 : RegisterClass<"Mips", [f64], 64, (add
434 def MSA128B: RegisterClass<"Mips", [v16i8], 128,
436 def MSA128H: RegisterClass<"Mips", [v8i16, v8f16], 128,
438 def MSA128W: RegisterClass<"Mips", [v4i32, v4f32], 128,
[all …]
/llvm-project-15.0.7/llvm/lib/Target/SPIRV/
H A DSPIRVRegisterInfo.td19 def TYPE : RegisterClass<"SPIRV", [i32], 32, (add TYPE0)>;
23 def ID : RegisterClass<"SPIRV", [i32], 32, (add ID0)>;
25 def fID : RegisterClass<"SPIRV", [f32], 32, (add fID0)>;
27 def pID : RegisterClass<"SPIRV", [p0], 32, (add pID0)>;
29 def vID : RegisterClass<"SPIRV", [v2i32], 32, (add vID0)>;
31 def vfID : RegisterClass<"SPIRV", [v2f32], 32, (add vfID0)>;
33 …def ANYID : RegisterClass<"SPIRV", [i32, f32, p0, v2i32, v2f32], 32, (add ID, fID, pID, vID, vfID)…
38 def ANY : RegisterClass<"SPIRV", [i32], 32, (add TYPE, ID)>;
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonPatternsV65.td9 multiclass vgathermh<RegisterClass RC> {
19 multiclass vgathermw<RegisterClass RC> {
29 multiclass vgathermhw<RegisterClass RC> {
43 multiclass vgathermhq<RegisterClass RC1, RegisterClass RC2> {
54 multiclass vgathermwq<RegisterClass RC1, RegisterClass RC2> {
65 multiclass vgathermhwq<RegisterClass RC1, RegisterClass RC2> {
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMRegisterInfo.td262 def GPRnopc : RegisterClass<"ARM", [i32], 32, (sub GPR, PC)> {
318 def GPRsp : RegisterClass<"ARM", [i32], 32, (add SP)> {
324 def GPRlr : RegisterClass<"ARM", [i32], 32, (add LR)>;
330 def rGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, SP, PC)> {
352 def tGPR : RegisterClass<"ARM", [i32], 32, (trunc GPR, 8)> {
361 def hGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, tGPR)> {
394 def CCR : RegisterClass<"ARM", [i32], 32, (add CPSR)> {
566 def QQPR : RegisterClass<"ARM", [v4i64], 256, (add Tuples2Q)> {
573 def MQQPR : RegisterClass<"ARM", [v4i64], 256, (trunc QQPR, 7)>;
583 def DQuad : RegisterClass<"ARM", [v4i64], 256,
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.td114 def GPR8 : RegisterClass<"AVR", [i8], 8,
125 def GPR8lo : RegisterClass<"AVR", [i8], 8,
130 def LD8 : RegisterClass<"AVR", [i8], 8,
140 def LD8lo : RegisterClass<"AVR", [i8], 8,
144 def DREGS : RegisterClass<"AVR", [i16], 8,
159 : RegisterClass<"AVR", [i16], 8,
163 def DREGSLD8lo : RegisterClass<"AVR", [i16], 8,
171 def DREGSMOVW : RegisterClass<"AVR", [i16], 8,
182 def DLDREGS : RegisterClass<"AVR", [i16], 8,
192 def IWREGS : RegisterClass<"AVR", [i16], 8,
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/llvm-project-15.0.7/llvm/test/TableGen/
H A Dambiguous-composition.td66 def FP32 : RegisterClass<"FP32", [f32], 32, (add F0S)>;
67 def FP64 : RegisterClass<"FP64", [f64], 64, (add F0D)>;
68 def FP128 : RegisterClass<"FP128", [v2f64], 128, (add F0Q)>;
69 def VP128 : RegisterClass<"VP128", [v2f64], 128, (add V0Q)>;
90 def GP32 : RegisterClass<"GP32", [i32], 32, (add G0S)>;
91 def GP64 : RegisterClass<"GP64", [i64], 64, (add G0D)>;
92 def GP128 : RegisterClass<"GP128", [v2i64], 128, (add G0Q)>;
H A Drc-weight-override.td10 def GPR_64_W0 : RegisterClass<"", [v2i32], 64, (add GPR64)> {
15 def GPR_64_W1 : RegisterClass<"", [v2i32], 64, (add GPR64)> {
20 def GPR_64_W8 : RegisterClass<"", [v2i32], 64, (add GPR64)> {
H A DTreeNames.td6 class RegisterClass;
11 def R32 : RegisterClass;
H A DRegisterBankEmitter.td8 def ClassA : RegisterClass<"MyTarget", [i32], 32, (add R0)>;
9 def ClassB : RegisterClass<"MyTarget", [i1], 32, (add ClassA)>;
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYRegisterInfo.td152 def GPR : RegisterClass<"CSKY", [i32], 32,
162 def sGPR : RegisterClass<"CSKY", [i32], 32,
170 def mGPR : RegisterClass<"CSKY", [i32], 32,
176 def GPRSP : RegisterClass<"CSKY", [i32], 32, (add R14)> {
184 def CARRY : RegisterClass<"CSKY", [i32], 32, (add C)> {
191 def FPR32 : RegisterClass<"CSKY", [f32], 32,
193 def sFPR32 : RegisterClass<"CSKY", [f32], 32,
196 def FPR64 : RegisterClass<"CSKY", [f64], 32,
198 def sFPR64 : RegisterClass<"CSKY", [f64], 32,
203 def FPR128 : RegisterClass<"CSKY",
[all …]
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchFloatInstrFormats.td160 class FP_ALU_2R<bits<22> op, string opstr, RegisterClass rc>
163 class FP_ALU_3R<bits<17> op, string opstr, RegisterClass rc>
166 class FP_ALU_4R<bits<12> op, string opstr, RegisterClass rc>
178 class FP_CMP<FPCMPOpc op, FPCMPCond cond, string opstr, RegisterClass rc>
182 class FP_CONV<bits<22> op, string opstr, RegisterClass rcd, RegisterClass rcs>
185 class FP_MOV<bits<22> op, string opstr, RegisterClass rcd, RegisterClass rcs>
188 class FP_SEL<bits<14> op, string opstr, RegisterClass rc>
200 class FP_LOAD_3R<bits<17> op, string opstr, RegisterClass rc>
203 class FP_LOAD_2RI12<bits<10> op, string opstr, RegisterClass rc>
209 class FP_STORE_3R<bits<17> op, string opstr, RegisterClass rc>
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/llvm-project-15.0.7/llvm/test/TableGen/Common/
H A DGlobalISelEmitterCommon.td10 def GPR32 : RegisterClass<"MyTarget", [i32], 32, (add R0)>;
13 def FPR32 : RegisterClass<"MyTarget", [f32], 32, (add F0)>;
16 def GPR8 : RegisterClass<"MyTarget", [i8], 8, (add B0)>;
21 def VecReg128 : RegisterClass<"MyTarget", [v4i32], 128, (add V0)>;
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/X86/
H A Dreg-usage.ll15 ; CHECK-NEXT: LV(REG): RegisterClass: Generic::ScalarRC, 2 registers
16 ; CHECK-NEXT: LV(REG): RegisterClass: Generic::VectorRC, 7 registers
20 ; CHECK-NEXT: LV(REG): RegisterClass: Generic::ScalarRC, 2 registers
21 ; CHECK-NEXT: LV(REG): RegisterClass: Generic::VectorRC, 13 registers
57 ; CHECK-NEXT: LV(REG): RegisterClass: Generic::ScalarRC, 2 registers
58 ; CHECK-NEXT: LV(REG): RegisterClass: Generic::VectorRC, 7 registers
62 ; CHECK-NEXT: LV(REG): RegisterClass: Generic::ScalarRC, 2 registers
63 ; CHECK-NEXT: LV(REG): RegisterClass: Generic::VectorRC, 13 registers
97 ; CHECK-NEXT: LV(REG): RegisterClass: Generic::VectorRC, 3 registers
98 ; CHECK-NEXT: LV(REG): RegisterClass: Generic::ScalarRC, 1 registers
[all …]
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEInstrVec.td469 multiclass VBRDm<string opcStr, bits<8>opc, RegisterClass VRC, RegisterClass RC,
514 RegisterClass RCM> {
556 multiclass RVm<string opcStr, bits<8>opc, RegisterClass VRC, RegisterClass RC,
569 RegisterClass RC, RegisterClass RCM, Operand SIMM = simm7> {
585 RegisterClass RC, RegisterClass RCM> {
597 RegisterClass RCM> {
605 RegisterClass RCM> {
613 RegisterClass RC, RegisterClass RCM> {
662 multiclass RVMm<string opcStr, bits<8>opc, RegisterClass VRC, RegisterClass RC,
713 RegisterClass RC> {
[all …]
H A DVERegisterInfo.td77 def MISC : RegisterClass<"VE", [i64], 64,
95 def VLS : RegisterClass<"VE", [i32], 64, (add VL)>;
170 def I32 : RegisterClass<"VE", [i32], 32,
174 def I64 : RegisterClass<"VE", [i64, f64], 64,
178 def F32 : RegisterClass<"VE", [f32], 32,
182 def F128 : RegisterClass<"VE", [f128], 128,
187 def V64 : RegisterClass<"VE",
195 def VM : RegisterClass<"VE", [v256i1], 64, (sequence "VM%u", 0, 15)>;
196 def VM512 : RegisterClass<"VE", [v512i1], 64, (sequence "VMP%u", 0, 7)>;
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.td153 def GPR64common : RegisterClass<"AArch64", [i64], 64,
179 def GPR64sponly : RegisterClass<"AArch64", [i64], 64, (add SP)>;
249 def CCR : RegisterClass<"AArch64", [i32], 32, (add NZCV)> {
447 def FPR64_lo : RegisterClass<"AArch64",
455 def FPR128 : RegisterClass<"AArch64",
462 def FPR128_lo : RegisterClass<"AArch64",
547 multiclass VectorList<int count, RegisterClass Reg64, RegisterClass Reg128> {
695 def WSeqPairsClass : RegisterClass<"AArch64", [untyped], 32,
854 RegisterClass RC> : RegisterOperand<RC> {
872 class PPRClass<int lastreg> : RegisterClass<
[all …]
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.td126 def GPR : RegisterClass<"RISCV", [XLenVT], 32, (add
157 def GPRC : RegisterClass<"RISCV", [XLenVT], 32, (add
168 def GPRTC : RegisterClass<"RISCV", [XLenVT], 32, (add
228 def FPR16 : RegisterClass<"RISCV", [f16], 16, (add
236 def FPR32 : RegisterClass<"RISCV", [f32], 32, (add
244 def FPR32C : RegisterClass<"RISCV", [f32], 32, (add
251 def FPR64 : RegisterClass<"RISCV", [f64], 64, (add
259 def FPR64C : RegisterClass<"RISCV", [f64], 64, (add
465 def VCSR : RegisterClass<"RISCV", [XLenVT], 32,
483 : RegisterClass<"RISCV",
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/PowerPC/
H A Dreg-usage.ll135 ;CHECK-NEXT: LV(REG): RegisterClass: PPC::GPRRC, 2 registers
136 ;CHECK-NEXT: LV(REG): RegisterClass: PPC::VSXRC, 3 registers
138 ;CHECK-NEXT: LV(REG): RegisterClass: PPC::GPRRC, 1 registers
175 ;CHECK-PWR8-NEXT: LV(REG): RegisterClass: PPC::GPRRC, 2 registers
176 ;CHECK-PWR8-NEXT: LV(REG): RegisterClass: PPC::VSXRC, 5 registers
178 ;CHECK-PWR8-NEXT: LV(REG): RegisterClass: PPC::VSXRC, 1 registers
182 ;CHECK-PWR9-NEXT: LV(REG): RegisterClass: PPC::GPRRC, 2 registers
227 ;CHECK: LV(REG): RegisterClass: PPC::GPRRC, 2 registers
228 ;CHECK: LV(REG): RegisterClass: PPC::VRRC, 2 registers
251 ;CHECK: LV(REG): RegisterClass: PPC::GPRRC, 4 registers
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/AArch64/
H A Di1-reg-usage.ll11 ; CHECK-NEXT: LV(REG): RegisterClass: Generic::VectorRC, 72 registers
12 ; CHECK-NEXT: LV(REG): RegisterClass: Generic::ScalarRC, 1 registers
34 ; CHECK-NEXT: LV(REG): RegisterClass: Generic::VectorRC, 136 registers
35 ; CHECK-NEXT: LV(REG): RegisterClass: Generic::ScalarRC, 1 registers
/llvm-project-15.0.7/llvm/include/llvm/Target/GlobalISel/
H A DRegisterBank.td12 class RegisterBank<string name, list<RegisterClass> classes> {
14 list<RegisterClass> RegisterClasses = classes;
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.td348 def F4RC : RegisterClass<"PPC", [f32], 32, (add F8RC)>;
350 def VRRC : RegisterClass<"PPC",
366 def VFRC : RegisterClass<"PPC", [f64], 64,
380 def VSSRC : RegisterClass<"PPC", [f32], 32, (add VSFRC)>;
382 def CRBITRC : RegisterClass<"PPC", [i1], 32,
400 def CRRC : RegisterClass<"PPC", [i32], 32,
412 def CTRRC : RegisterClass<"PPC", [i32], 32, (add CTR)> {
415 def CTRRC8 : RegisterClass<"PPC", [i64], 64, (add CTR8)> {
419 def LRRC : RegisterClass<"PPC", [i32], 32, (add LR)> {
422 def LR8RC : RegisterClass<"PPC", [i64], 64, (add LR8)> {
[all …]

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