Lines Matching refs:RegisterClass
227 def GPR : RegisterClass<"ARM", [i32], 32, (add (sequence "R%u", 0, 12),
245 def GPRnoip : RegisterClass<"ARM", [i32], 32, (sub GPR, R12, LR)> {
262 def GPRnopc : RegisterClass<"ARM", [i32], 32, (sub GPR, PC)> {
274 def GPRwithAPSR : RegisterClass<"ARM", [i32], 32, (add (sub GPR, PC), APSR_NZCV)> {
283 def GPRnosp : RegisterClass<"ARM", [i32], 32, (add (sequence "R%u", 0, 12), LR, PC)> {
293 def GPRwithAPSRnosp : RegisterClass<"ARM", [i32], 32, (add (sequence "R%u", 0, 12), LR, APSR)> {
297 def GPRwithZR : RegisterClass<"ARM", [i32], 32, (add (sub GPR, PC), ZR)> {
305 def GPRwithZRnosp : RegisterClass<"ARM", [i32], 32, (sub GPRwithZR, SP)> {
318 def GPRsp : RegisterClass<"ARM", [i32], 32, (add SP)> {
324 def GPRlr : RegisterClass<"ARM", [i32], 32, (add LR)>;
330 def rGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, SP, PC)> {
344 : RegisterClass<"ARM", [i32], 32, (add (sequence "R%u", 0, 12), LR, APSR_NZCV)> {
352 def tGPR : RegisterClass<"ARM", [i32], 32, (trunc GPR, 8)> {
358 def tGPRwithpc : RegisterClass<"ARM", [i32], 32, (add tGPR, PC)>;
361 def hGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, tGPR)> {
369 def tcGPR : RegisterClass<"ARM", [i32], 32, (add R0, R1, R2, R3, R12)> {
376 def tGPROdd : RegisterClass<"ARM", [i32], 32, (add R1, R3, R5, R7, R9, R11)> {
385 def tGPREven : RegisterClass<"ARM", [i32], 32, (add R0, R2, R4, R6, R8, R10, R12, LR)> {
394 def CCR : RegisterClass<"ARM", [i32], 32, (add CPSR)> {
400 def VCCR : RegisterClass<"ARM", [i32, v16i1, v8i1, v4i1, v2i1], 32, (add VPR)> {
406 def cl_FPSCR_NZCV : RegisterClass<"ARM", [i32], 32, (add FPSCR_NZCV)>;
412 def SPR : RegisterClass<"ARM", [f32], 32, (sequence "S%u", 0, 31)> {
424 def HPR : RegisterClass<"ARM", [f16, bf16], 32, (sequence "S%u", 0, 31)> {
438 def SPR_8 : RegisterClass<"ARM", [f32], 32, (sequence "S%u", 0, 15)> {
446 def DPR : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32, v4f16, v4bf16], 64,
461 def FPWithVPR : RegisterClass<"ARM", [f32], 32, (add SPR, DPR, VPR)> {
467 def DPR_VFP2 : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32, v4f16, v4bf16], 64,
474 def DPR_8 : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32, v4f16, v4bf16], 64,
480 def QPR : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64, v8f16, v8bf16], 128,
491 def QPR_VFP2 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
497 def QPR_8 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
505 def MQPR : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64, v8f16],
518 def DPair : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
539 def GPRPair : RegisterClass<"ARM", [untyped], 64, (add Tuples2Rnosp, Tuples2Rsp)> {
544 def GPRPairnosp : RegisterClass<"ARM", [untyped], 64, (add Tuples2Rnosp)> {
555 def DTriple : RegisterClass<"ARM", [untyped], 64, (add Tuples3D)> {
566 def QQPR : RegisterClass<"ARM", [v4i64], 256, (add Tuples2Q)> {
573 def MQQPR : RegisterClass<"ARM", [v4i64], 256, (trunc QQPR, 7)>;
583 def DQuad : RegisterClass<"ARM", [v4i64], 256,
592 def QQQQPR : RegisterClass<"ARM", [v8i64], 256, (add Tuples2QQ)> {
599 def MQQQQPR : RegisterClass<"ARM", [v8i64], 256, (trunc QQQQPR, 5)>;
608 def DPairSpc : RegisterClass<"ARM", [v2i64], 64, (add Tuples2DSpc)>;
616 def DTripleSpc : RegisterClass<"ARM", [untyped], 64, (add Tuples3DSpc)> {
627 def DQuadSpc : RegisterClass<"ARM", [v4i64], 64, (add Tuples3DSpc)>;
630 def FPCXTRegs : RegisterClass<"ARM", [i32], 32, (add FPCXTNS)>;