Lines Matching refs:RegisterClass
281 def GPRC : RegisterClass<"PPC", [i32,f32], 32, (add (sequence "R%u", 2, 12),
297 def G8RC : RegisterClass<"PPC", [i64], 64, (add (sequence "X%u", 2, 12),
313 def GPRC_NOR0 : RegisterClass<"PPC", [i32,f32], 32, (add (sub GPRC, R0), ZERO)> {
324 def G8RC_NOX0 : RegisterClass<"PPC", [i64], 64, (add (sub G8RC, X0), ZERO8)> {
335 def SPERC : RegisterClass<"PPC", [f64], 64, (add (sequence "S%u", 2, 12),
346 def F8RC : RegisterClass<"PPC", [f64], 64, (add (sequence "F%u", 0, 13),
348 def F4RC : RegisterClass<"PPC", [f32], 32, (add F8RC)>;
350 def VRRC : RegisterClass<"PPC",
359 def VSLRC : RegisterClass<"PPC", [v4i32,v4f32,v2f64,v2i64], 128,
362 def VSRC : RegisterClass<"PPC", [v4i32,v4f32,v2f64,v2i64], 128,
366 def VFRC : RegisterClass<"PPC", [f64], 64,
372 def VSFRC : RegisterClass<"PPC", [f64], 64, (add F8RC, VFRC)>;
375 def SPILLTOVSRRC : RegisterClass<"PPC", [i64, f64], 64, (add G8RC, (sub VSFRC,
380 def VSSRC : RegisterClass<"PPC", [f32], 32, (add VSFRC)>;
382 def CRBITRC : RegisterClass<"PPC", [i1], 32,
400 def CRRC : RegisterClass<"PPC", [i32], 32,
412 def CTRRC : RegisterClass<"PPC", [i32], 32, (add CTR)> {
415 def CTRRC8 : RegisterClass<"PPC", [i64], 64, (add CTR8)> {
419 def LRRC : RegisterClass<"PPC", [i32], 32, (add LR)> {
422 def LR8RC : RegisterClass<"PPC", [i64], 64, (add LR8)> {
426 def VRSAVERC : RegisterClass<"PPC", [i32], 32, (add VRSAVE)>;
427 def CARRYRC : RegisterClass<"PPC", [i32], 32, (add CARRY, XER)> {
435 RegisterClass<"PPC", [i128], 128,
456 // directly on the RegisterClass, all instructions patterns used by the asm
457 // parser need to use a RegisterOperand (instead of a RegisterClass) for
459 // For this purpose, we define one RegisterOperand for each RegisterClass,