| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | RegisterBank.cpp | 22 const unsigned RegisterBank::InvalidID = UINT_MAX;
24 RegisterBank::RegisterBank( in RegisterBank() function in RegisterBank
32 bool RegisterBank::verify(const TargetRegisterInfo &TRI) const { in verify()
61 bool RegisterBank::covers(const TargetRegisterClass &RC) const { in covers()
66 bool RegisterBank::isValid() const { in isValid()
72 bool RegisterBank::operator==(const RegisterBank &OtherRB) const { in operator ==()
82 LLVM_DUMP_METHOD void RegisterBank::dump(const TargetRegisterInfo *TRI) const { in dump()
87 void RegisterBank::print(raw_ostream &OS, bool IsForDebug, in print()
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| H A D | RegisterBankInfo.cpp | 55 RegisterBankInfo::RegisterBankInfo(RegisterBank **RegBanks, in RegisterBankInfo()
69 const RegisterBank &RegBank = getRegBank(Idx); in verify()
79 const RegisterBank *
90 if (auto *RB = RegClassOrBank.dyn_cast<const RegisterBank *>()) in getRegBank()
109 const RegisterBank *RegisterBankInfo::getRegBankFromConstraints( in getRegBankFromConstraints()
137 const RegisterBank *RB = RegClassOrBank.get<const RegisterBank *>(); in constrainGenericRegister()
193 const RegisterBank *AltRegBank = getRegBank(Reg, MRI, TRI); in getInstrMappingImpl()
197 const RegisterBank *CurRegBank = IsCopyLike ? AltRegBank : nullptr; in getInstrMappingImpl()
238 const RegisterBank *AltRegBank = getRegBank(Reg, MRI, TRI); in getInstrMappingImpl()
265 const RegisterBank *RegBank) { in hashPartialMapping()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | RegisterBankInfo.h | 33 class RegisterBank; variable
60 const RegisterBank *RegBank;
66 const RegisterBank &RegBank) in PartialMapping()
387 RegisterBank **RegBanks;
431 RegisterBank &getRegBank(unsigned ID) { in getRegBank()
544 const RegisterBank *
575 const RegisterBank &getRegBank(unsigned ID) const { in getRegBank()
602 virtual const RegisterBank &
613 virtual unsigned copyCost(const RegisterBank &A, const RegisterBank &B, in copyCost()
623 bool cannotCopy(const RegisterBank &Dst, const RegisterBank &Src, in cannotCopy()
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| H A D | RegisterBank.h | 28 class RegisterBank {
43 RegisterBank(unsigned ID, const char *Name, unsigned Size,
74 bool operator==(const RegisterBank &OtherRB) const;
75 bool operator!=(const RegisterBank &OtherRB) const {
92 inline raw_ostream &operator<<(raw_ostream &OS, const RegisterBank &RegBank) {
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| /llvm-project-15.0.7/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVRegisterBanks.td | 11 def IDRegBank : RegisterBank<"IDBank", [ID]>;
12 def fIDRegBank : RegisterBank<"fIDBank", [fID]>;
13 def vIDRegBank : RegisterBank<"vIDBank", [vID]>;
14 def vfIDRegBank : RegisterBank<"vfIDBank", [vfID]>;
15 def TYPERegBank : RegisterBank<"TYPEBank", [TYPE]>;
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| H A D | SPIRVRegisterBankInfo.h | 34 const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC,
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| H A D | SPIRVRegisterBankInfo.cpp | 27 const RegisterBank &
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| /llvm-project-15.0.7/llvm/utils/TableGen/ |
| H A D | RegisterBankEmitter.cpp | 28 class RegisterBank { class
43 RegisterBank(const Record &TheDef) in RegisterBank() function in __anon92a9f3a60111::RegisterBank
108 const std::vector<RegisterBank> &Banks);
110 const std::vector<RegisterBank> &Banks);
112 std::vector<RegisterBank> &Banks);
126 const std::vector<RegisterBank> &Banks) { in emitHeader()
145 const std::vector<RegisterBank> &Banks) { in emitBaseClassDefinition()
212 std::vector<RegisterBank> &Banks) { in emitBaseClassImplementation()
280 std::vector<RegisterBank> Banks; in run()
283 RegisterBank Bank(*V); in run()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegisterBanks.td | 9 def SGPRRegBank : RegisterBank<"SGPR",
13 def VGPRRegBank : RegisterBank<"VGPR",
18 def VCCRegBank : RegisterBank <"VCC", [SReg_1]>;
20 def AGPRRegBank : RegisterBank <"AGPR",
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| H A D | AMDGPURegisterBankInfo.h | 168 unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
172 const RegisterBank *CurBank = nullptr) const override;
174 const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC,
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| H A D | AMDGPURegisterBankInfo.cpp | 102 const RegisterBank *NewBank;
274 const RegisterBank &
1057 const RegisterBank *DstBank = in applyMappingLoad()
1469 const RegisterBank *DstBank = in applyMappingBFE()
1628 const RegisterBank &DstBank = in applyMappingMAD_64_32()
1932 const RegisterBank &IdxBank = in foldExtractEltToCmpSelect()
1948 const RegisterBank &DstBank = in foldExtractEltToCmpSelect()
1950 const RegisterBank &SrcBank = in foldExtractEltToCmpSelect()
1953 const RegisterBank &CCBank = in foldExtractEltToCmpSelect()
2030 const RegisterBank &IdxBank = in foldInsertEltToCmpSelect()
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| H A D | SIRegisterInfo.h | 27 class RegisterBank; variable
320 getRegClassForSizeOnBank(unsigned Size, const RegisterBank &Bank) const;
323 getRegClassForTypeOnBank(LLT Ty, const RegisterBank &Bank) const { in getRegClassForTypeOnBank()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64RegisterBankInfo.h | 65 unsigned ValLength, const RegisterBank &RB);
136 unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
139 const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC,
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| H A D | AArch64RegisterBankInfo.cpp | 55 const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID); in AArch64RegisterBankInfo()
60 const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID); in AArch64RegisterBankInfo()
65 const RegisterBank &RBCCR = getRegBank(AArch64::CCRegBankID); in AArch64RegisterBankInfo()
215 unsigned AArch64RegisterBankInfo::copyCost(const RegisterBank &A, in copyCost()
216 const RegisterBank &B, in copyCost()
236 const RegisterBank &
634 const RegisterBank *DstRB = getRegBank(DstReg, MRI, TRI); in getInstrMapping()
635 const RegisterBank *SrcRB = getRegBank(SrcReg, MRI, TRI); in getInstrMapping()
659 const RegisterBank &DstRB = in getInstrMapping()
661 const RegisterBank &SrcRB = in getInstrMapping()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64RegisterBanks.td | 13 def GPRRegBank : RegisterBank<"GPR", [XSeqPairsClass]>;
16 def FPRRegBank : RegisterBank<"FPR", [QQQQ]>;
19 def CCRegBank : RegisterBank<"CC", [CCR]>;
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/MIRParser/ |
| H A D | MIParser.h | 29 class RegisterBank; variable
44 const RegisterBank *RegBank;
51 using Name2RegBankMap = StringMap<const RegisterBank *>;
149 const RegisterBank *getRegBank(StringRef Name);
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsRegisterBanks.td | 12 def GPRBRegBank : RegisterBank<"GPRB", [GPR32]>;
14 def FPRBRegBank : RegisterBank<"FPRB", [FGR64, AFGR64, MSA128D]>;
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| /llvm-project-15.0.7/llvm/include/llvm/Target/GlobalISel/ |
| H A D | RegisterBank.td | 1 //===- RegisterBank.td - Register bank definitions ---------*- tablegen -*-===//
12 class RegisterBank<string name, list<RegisterClass> classes> {
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMRegisterBanks.td | 12 def GPRRegBank : RegisterBank<"GPRB", [GPR, GPRwithAPSR]>;
13 def FPRRegBank : RegisterBank<"FPRB", [HPR, SPR, DPR, QPR]>;
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| H A D | ARMRegisterBankInfo.h | 35 const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC,
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86RegisterBanks.td | 13 def GPRRegBank : RegisterBank<"GPR", [GR64]>;
16 def VECRRegBank : RegisterBank<"VECR", [VR512]>;
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| H A D | X86InstructionSelector.cpp | 202 const RegisterBank &RegBank = *RBI.getRegBank(Reg, MRI, TRI); in getRegClass()
238 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in selectCopy()
242 const RegisterBank &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in selectCopy()
512 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI); in selectLoadStoreOp()
721 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in selectTruncOrPtrToInt()
722 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI); in selectTruncOrPtrToInt()
850 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in selectAnyext()
851 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI); in selectAnyext()
1325 const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI); in selectMergeValues()
1394 const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI); in materializeFP()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | CSEInfo.h | 164 class RegisterBank; variable
181 const GISelInstProfileBuilder &addNodeIDRegType(const RegisterBank *RB) const;
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| /llvm-project-15.0.7/llvm/lib/Target/M68k/GISel/ |
| H A D | M68kRegisterBankInfo.h | 38 const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC,
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVRegisterBanks.td | 13 def GPRRegBank : RegisterBank<"GPRB", [GPR]>;
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