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Searched refs:RegUnit (Results 1 – 22 of 22) sorted by relevance

/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DRegisterPressure.cpp363 Register RegUnit = Pair.RegUnit; in initLiveThru() local
374 return Other.RegUnit == RegUnit; in getRegLanes()
383 Register RegUnit = Pair.RegUnit; in addRegLanes() local
386 return Other.RegUnit == RegUnit; in addRegLanes()
398 return Other.RegUnit == RegUnit; in setRegZero()
409 Register RegUnit = Pair.RegUnit; in removeRegLanes() local
412 return Other.RegUnit == RegUnit; in removeRegLanes()
610 Register RegUnit = I->RegUnit; in adjustLaneLiveness() local
636 Register RegUnit = P.RegUnit; in adjustLaneLiveness() local
719 Register RegUnit = Pair.RegUnit; in discoverLiveInOrOut() local
[all …]
H A DLiveRegMatrix.cpp179 MCRegister RegUnit) { in query() argument
180 LiveIntervalUnion::Query &Q = Queries[RegUnit]; in query()
181 Q.init(UserTag, LR, Matrix[RegUnit]); in query()
H A DMachineCopyPropagation.cpp207 MachineInstr *findCopyForUnit(MCRegister RegUnit, in findCopyForUnit() argument
210 auto CI = Copies.find(RegUnit); in findCopyForUnit()
218 MachineInstr *findCopyDefViaUnit(MCRegister RegUnit, in findCopyDefViaUnit() argument
220 auto CI = Copies.find(RegUnit); in findCopyDefViaUnit()
H A DMachineTraceMetrics.cpp1143 TBI.LiveIns.push_back(LiveInReg(RI->RegUnit, RI->Cycle)); in computeInstrHeights()
1144 LLVM_DEBUG(dbgs() << ' ' << printRegUnit(RI->RegUnit, MTM.TRI) << '@' in computeInstrHeights()
H A DMachineScheduler.cpp1117 Register Reg = P.RegUnit; in updatePressureDiffs()
1342 Register Reg = P.RegUnit; in computeCyclicCriticalPath()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DRegisterPressure.h39 Register RegUnit; ///< Virtual register or register unit. member
42 RegisterMaskPair(Register RegUnit, LaneBitmask LaneMask) in RegisterMaskPair()
43 : RegUnit(RegUnit), LaneMask(LaneMask) {} in RegisterMaskPair()
159 void addPressureChange(Register RegUnit, bool IsDec,
305 unsigned SparseIndex = getSparseIndexFromReg(Pair.RegUnit); in insert()
318 unsigned SparseIndex = getSparseIndexFromReg(Pair.RegUnit); in erase()
550 void increaseRegPressure(Register RegUnit, LaneBitmask PreviousMask,
552 void decreaseRegPressure(Register RegUnit, LaneBitmask PreviousMask,
563 LaneBitmask getLastUsedLanes(Register RegUnit, SlotIndex Pos) const;
564 LaneBitmask getLiveLanesAt(Register RegUnit, SlotIndex Pos) const;
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H A DMachineTraceMetrics.h76 unsigned RegUnit; member
81 unsigned getSparseSetIndex() const { return RegUnit; } in getSparseSetIndex()
83 LiveRegUnit(unsigned RU) : RegUnit(RU) {} in LiveRegUnit()
H A DMachineRegisterInfo.h633 PSetIterator getPressureSets(Register RegUnit) const;
1209 PSetIterator(Register RegUnit, const MachineRegisterInfo *MRI) { in PSetIterator() argument
1211 if (RegUnit.isVirtual()) { in PSetIterator()
1212 const TargetRegisterClass *RC = MRI->getRegClass(RegUnit); in PSetIterator()
1216 PSet = TRI->getRegUnitPressureSets(RegUnit); in PSetIterator()
1217 Weight = TRI->getRegUnitWeight(RegUnit); in PSetIterator()
1238 MachineRegisterInfo::getPressureSets(Register RegUnit) const { in getPressureSets() argument
1239 return PSetIterator(RegUnit, this); in getPressureSets()
H A DTargetRegisterInfo.h428 bool hasRegUnit(MCRegister Reg, Register RegUnit) const { in hasRegUnit() argument
430 if (Register(*Units) == RegUnit) in hasRegUnit()
823 virtual unsigned getRegUnitWeight(unsigned RegUnit) const = 0;
843 virtual const int *getRegUnitPressureSets(unsigned RegUnit) const = 0;
H A DLiveRegMatrix.h153 LiveIntervalUnion::Query &query(const LiveRange &LR, MCRegister RegUnit);
/llvm-project-15.0.7/llvm/utils/TableGen/
H A DCodeGenRegisters.h501 struct RegUnit { struct
519 RegUnit() : Weight(0), RegClassUnitSetsIdx(0), Artificial(false) { in RegUnit() function
570 SmallVector<RegUnit, 8> RegUnits;
708 RegUnit &RU = RegUnits.back();
736 RegUnit &getRegUnit(unsigned RUID) { return RegUnits[RUID]; } in getRegUnit()
737 const RegUnit &getRegUnit(unsigned RUID) const { return RegUnits[RUID]; } in getRegUnit()
H A DCodeGenRegisters.cpp590 for (unsigned RegUnit : RegUnits) { in getWeight() local
591 Weight += RegBank.getRegUnit(RegUnit).Weight; in getWeight()
1123 const RegUnit &RU = RegBank.getRegUnit(*UnitI); in buildRegUnitSet()
H A DRegisterInfoEmitter.cpp250 const RegUnit &RU = RegBank.getRegUnit(UnitIdx); in EmitRegUnitPressure()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DGCNRegPressure.cpp232 Res, [Reg](const RegisterMaskPair &RM) { return RM.RegUnit == Reg; }); in collectVirtualRegUses()
312 auto LiveMask = LiveRegs[U.RegUnit]; in recede()
313 AtMIPressure.inc(U.RegUnit, LiveMask, LiveMask | U.LaneMask, *MRI); in recede()
334 auto &LiveMask = LiveRegs[U.RegUnit]; in recede()
337 CurPressure.inc(U.RegUnit, PrevMask, LiveMask, *MRI); in recede()
H A DSIOptimizeExecMaskingPreRA.cpp353 LiveRange &RegUnit = LIS->getRegUnit(*UI); in optimizeElseBranch() local
354 if (RegUnit.find(StartIdx) != std::prev(RegUnit.find(EndIdx))) in optimizeElseBranch()
H A DSIMachineScheduler.h468 InRegs.insert(RegMaskPair.RegUnit); in getInRegs()
476 OutRegs.insert(RegMaskPair.RegUnit); in getOutRegs()
H A DSIWholeQuadMode.cpp456 for (MCRegUnitIterator RegUnit(Reg.asMCReg(), TRI); RegUnit.isValid(); in markOperand() local
457 ++RegUnit) { in markOperand()
458 LiveRange &LR = LIS->getRegUnit(*RegUnit); in markOperand()
463 markDefs(MI, LR, *RegUnit, AMDGPU::NoSubRegister, Flag, Worklist); in markOperand()
H A DSIRegisterInfo.h315 const int *getRegUnitPressureSets(unsigned RegUnit) const override;
H A DSIMachineScheduler.cpp332 if (Register::isVirtualRegister(RegMaskPair.RegUnit)) in initRegPressure()
333 LiveInRegs.insert(RegMaskPair.RegUnit); in initRegPressure()
359 Register Reg = RegMaskPair.RegUnit; in initRegPressure()
H A DSIRegisterInfo.cpp2886 const int *SIRegisterInfo::getRegUnitPressureSets(unsigned RegUnit) const { in getRegUnitPressureSets()
2889 if (RegPressureIgnoredUnits[RegUnit]) in getRegUnitPressureSets()
2892 return AMDGPUGenRegisterInfo::getRegUnitPressureSets(RegUnit); in getRegUnitPressureSets()
/llvm-project-15.0.7/llvm/include/llvm/MC/
H A DMCRegisterInfo.h761 MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI) { in MCRegUnitRootIterator() argument
762 assert(RegUnit < MCRI->getNumRegUnits() && "Invalid register unit"); in MCRegUnitRootIterator()
763 Reg0 = MCRI->RegUnitRoots[RegUnit][0]; in MCRegUnitRootIterator()
764 Reg1 = MCRI->RegUnitRoots[RegUnit][1]; in MCRegUnitRootIterator()
/llvm-project-15.0.7/llvm/unittests/CodeGen/
H A DMFCommon.inc45 unsigned getRegUnitWeight(unsigned RegUnit) const override { return 1; }
59 const int *getRegUnitPressureSets(unsigned RegUnit) const override {