Searched refs:RegBytes (Results 1 – 4 of 4) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86SpeculativeLoadHardening.cpp | 1868 int RegBytes = TRI->getRegSizeInBits(*RC) / 8; in canHardenRegister() local
1869 if (RegBytes > 8) in canHardenRegister()
1873 unsigned RegIdx = Log2_32(RegBytes); in canHardenRegister()
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| H A D | X86InstrInfo.h | 41 unsigned getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand = false);
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| H A D | X86InstrInfo.cpp | 2806 unsigned X86::getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand) { in getCMovOpcode() argument
2807 switch(RegBytes) { in getCMovOpcode()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 8401 unsigned RegBytes = RegVT.getSizeInBits() / 8; in expandUnalignedLoad() local
8402 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes; in expandUnalignedLoad()
8414 SDValue PtrIncrement = DAG.getConstant(RegBytes, dl, PtrVT); in expandUnalignedLoad()
8415 SDValue StackPtrIncrement = DAG.getConstant(RegBytes, dl, StackPtrVT); in expandUnalignedLoad()
8429 Offset += RegBytes; in expandUnalignedLoad()
8554 unsigned RegBytes = RegVT.getSizeInBits() / 8; in expandUnalignedStore() local
8555 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes; in expandUnalignedStore()
8568 SDValue PtrIncrement = DAG.getConstant(RegBytes, dl, PtrVT); in expandUnalignedStore()
8569 SDValue StackPtrIncrement = DAG.getConstant(RegBytes, dl, StackPtrVT); in expandUnalignedStore()
8585 Offset += RegBytes; in expandUnalignedStore()
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