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/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dflat-scratch-init.ll10 ; RO-FLAT-NOT: flat_scratch
14 ; RO-FLAT-NOT: .amdhsa_user_sgpr_flat_scratch_init
18 ; RO-FLAT: .amdhsa_enable_private_segment 1
22 ; RO-FLAT: COMPUTE_PGM_RSRC2:USER_SGPR: 0
32 ; RO-FLAT-NOT: flat_scratch
34 ; RO-FLAT: scratch_store_dword
42 ; RO-FLAT: .amdhsa_enable_private_segment 1
44 ; RO-FLAT-NOT: .amdhsa_reserve_flat_scratch
47 ; RO-FLAT: COMPUTE_PGM_RSRC2:USER_SGPR: 0
65 ; RO-FLAT-NOT: .amdhsa_reserve_flat_scratch 0
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/GlobalISel/
H A Darm-isel-globals-ropi-rwpi.ll73 ; RO-DEFAULT-NEXT: ldr r0, [r[[ADDR]]]
74 ; RO-DEFAULT-NEXT: bx lr
75 ; RO-DEFAULT-NOMOVT: [[LABEL]]:
76 ; RO-DEFAULT-NOMOVT-NEXT: .long internal_constant
99 ; RO-DEFAULT-NEXT: ldr r0, [r[[ADDR]]]
100 ; RO-DEFAULT-NEXT: bx lr
101 ; RO-DEFAULT-NOMOVT: [[LABEL]]:
102 ; RO-DEFAULT-NOMOVT: .long external_constant
120 ; RO-DEFAULT-NOMOVT: internal_constant:
121 ; RO-DEFAULT-NOMOVT: .long 42
[all …]
H A Dthumb-isel-globals-ropi-rwpi.ll73 ; RO-DEFAULT-NEXT: ldr r0, [r[[ADDR]]]
74 ; RO-DEFAULT-NEXT: bx lr
75 ; RO-DEFAULT-NOMOVT: [[LABEL]]:
76 ; RO-DEFAULT-NOMOVT-NEXT: .long internal_constant
99 ; RO-DEFAULT-NEXT: ldr r0, [r[[ADDR]]]
100 ; RO-DEFAULT-NEXT: bx lr
101 ; RO-DEFAULT-NOMOVT: [[LABEL]]:
102 ; RO-DEFAULT-NOMOVT: .long external_constant
120 ; RO-DEFAULT-NOMOVT: internal_constant:
121 ; RO-DEFAULT-NOMOVT: .long 42
[all …]
H A Dthumb-select-globals-ropi-rwpi.mir3 …t -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,RWPI-MOVT,RWPI,RO-DEFAULT-MOVT
98 # RO-DEFAULT-NOMOVT: constants:
99 # RO-DEFAULT-NOMOVT: id: 0
100 # RO-DEFAULT-NOMOVT: value: 'ptr @internal_constant'
106 ; RO-DEFAULT-MOVT: [[G:%[0-9]+]]:rgpr = t2MOVi32imm @internal_constant
107 …; RO-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = t2LDRpci %const.0, 14 /* CC::al */, $noreg :: (load (p0) …
128 # RO-DEFAULT-NOMOVT: constants:
129 # RO-DEFAULT-NOMOVT: id: 0
130 # RO-DEFAULT-NOMOVT: value: 'ptr @external_constant'
136 ; RO-DEFAULT-MOVT: [[G:%[0-9]+]]:rgpr = t2MOVi32imm @external_constant
[all …]
H A Darm-select-globals-ropi-rwpi.mir3 …t -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,RWPI-MOVT,RWPI,RO-DEFAULT-MOVT
98 # RO-DEFAULT-NOMOVT: constants:
99 # RO-DEFAULT-NOMOVT: id: 0
100 # RO-DEFAULT-NOMOVT: value: 'ptr @internal_constant'
106 ; RO-DEFAULT-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @internal_constant
107 …; RO-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14 /* CC::al */, $noreg :: (load (p0)…
128 # RO-DEFAULT-NOMOVT: constants:
129 # RO-DEFAULT-NOMOVT: id: 0
130 # RO-DEFAULT-NOMOVT: value: 'ptr @external_constant'
136 ; RO-DEFAULT-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @external_constant
[all …]
/llvm-project-15.0.7/lld/test/ELF/
H A Dsection-symbol-gap.s14 # RUN: llvm-readelf -S -r -s %t.ro | FileCheck %s --check-prefix=RO
30 # RO: [Nr] Name Type Address
31 # RO-NEXT: [ 0]
32 # RO-NEXT: [ 1] .bss NOBITS 0000000000000000
34 # RO: R_X86_64_64 {{.*}} .bss + 1
36 # RO: Symbol table '.symtab' contains 3 entries:
37 # RO-NEXT: Num: Value Size Type Bind Vis Ndx Name
38 # RO-NEXT: 0: 0000000000000000 0 NOTYPE LOCAL DEFAULT UND
39 # RO-NEXT: 1: 0000000000000000 0 SECTION LOCAL DEFAULT 1 .bss
40 # RO-NEXT: 2: 0000000000000000 0 SECTION LOCAL DEFAULT 2 .text
H A Dformat-binary.test10 # RUN: llvm-readelf -h -S -s -x .data ro | FileCheck --check-prefix=RO %s
12 # RO: Machine: Advanced Micro Devices X86-64
13 # RO: Name Type Address Off Size ES Flg Lk Inf Al
14 # RO-NEXT: NULL 0000000000000000 000000 000000 00 0 0 0
15 # RO-NEXT: .data PROGBITS 0000000000000000 {{.*}} 00000c 00 WA 0 0 8
16 # RO: Value Size Type Bind Vis Ndx Name
17 # RO: 0000000000000000 0 OBJECT GLOBAL DEFAULT 1 _binary_d_t_txt_start
18 # RO-NEXT: 000000000000000c 0 OBJECT GLOBAL DEFAULT 1 _binary_d_t_txt_end
19 # RO-NEXT: 000000000000000c 0 OBJECT GLOBAL DEFAULT ABS _binary_d_t_txt_size
20 # RO: Hex dump of section '.data':
[all …]
H A Darm-symbol-ordering-file.s7 # RUN: llvm-objcopy --set-section-flags .bar=alloc,readonly %t.large.o %t.large.RO.o
13 # RUN: ld.lld --symbol-ordering-file %t_order.txt %t.large.RO.o -o %t2.large.RO.out
16 # RUN: llvm-nm -n %t2.large.RO.out | FileCheck --check-prefix=SMALL %s
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMicroMipsInstrInfo.td215 InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),
217 [(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
279 InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr),
287 InstSE<(outs RO:$dst), (ins RO:$rt, mem_simm9:$addr),
308 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, RO:$rt),
310 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
322 MicroMipsInst16<(outs RO:$dst), (ins RO:$rs, RO:$rt),
324 [(set RO:$dst, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
330 MicroMipsInst16<(outs RO:$rt), (ins RO:$rs),
332 [(set RO:$rt, (not RO:$rs))], II_NOT, FrmR>;
[all …]
H A DMipsInstrInfo.td1320 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
1322 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
1333 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
1352 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
1354 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
1371 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
1420 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
1475 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
1487 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
1799 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, SizeOpnd:$size, RO:$src),
[all …]
H A DMicroMipsDSPInstrInfo.td217 RegisterOperand RO, Operand ImmOpnd> {
218 dag OutOperandList = (outs RO:$rt);
219 dag InOperandList = (ins RO:$rs, ImmOpnd:$sa);
221 list<dag> Pattern = [(set RO:$rt, (OpNode RO:$rs, ImmPat:$sa))];
253 InstrItinClass itin, RegisterOperand RO> {
254 dag OutOperandList = (outs RO:$rd);
255 dag InOperandList = (ins RO:$rt, GPR32Opnd:$rs);
257 list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))];
325 class MFHI_MM_DESC_BASE<string instr_asm, RegisterOperand RO, SDNode OpNode,
328 dag InOperandList = (ins RO:$ac);
[all …]
H A DMipsDSPInstrInfo.td335 RegisterOperand RO> {
336 dag OutOperandList = (outs RO:$rd);
346 dag OutOperandList = (outs RO:$rd);
347 dag InOperandList = (ins RO:$rt, GPR32Opnd:$rs_sa);
349 list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs_sa))];
357 dag OutOperandList = (outs RO:$rd);
358 dag InOperandList = (ins RO:$rt, ImmOpnd:$rs_sa);
360 list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, ImmPat:$rs_sa))];
505 dag InOperandList = (ins RO:$ac);
513 class MTHI_DESC_BASE<string instr_asm, RegisterOperand RO,
[all …]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/AArch64/
H A Dbrbe.txt32 [0x08,0x92,0x11,0xd5] # expect failure: BRBIDR0_EL1 is RO
67 [0x12,0x80,0x11,0xd5] # expect failure: BRBINF0_EL1 is RO
74 [0x14,0x81,0x11,0xd5] # expect failure: BRBINF1_EL1 is RO
81 [0x16,0x82,0x11,0xd5] # expect failure: BRBINF2_EL1 is RO
88 [0x38,0x84,0x11,0xd5] # expect failure: BRBSRC4_EL1 is RO
95 [0x3a,0x88,0x11,0xd5] # expect failure: BRBSRC8_EL1 is RO
102 [0xbc,0x80,0x11,0xd5] # expect failure: BRBSRC16_EL1 is RO
109 [0x40,0x8a,0x11,0xd5] # expect failure: BRBTGT10_EL1 is RO
116 [0xc2,0x85,0x11,0xd5] # expect failure: BRBTGT21_EL1 is RO
123 [0xc4,0x8f,0x11,0xd5] # expect failure: BRBTGT31_EL1 is RO
/llvm-project-15.0.7/libcxx/lib/abi/
H A Dpowerpc-ibm-aix.libcxxabi.v1.stable.exceptions.nonew.abilist279 …_defined': True, 'name': '_ZNSt3__110adopt_lockE', 'storage_mapping_class': 'RO', 'type': 'OBJECT'}
292 …_defined': True, 'name': '_ZNSt3__110defer_lockE', 'storage_mapping_class': 'RO', 'type': 'OBJECT'}
322 …defined': True, 'name': '_ZNSt3__111try_to_lockE', 'storage_mapping_class': 'RO', 'type': 'OBJECT'}
681 …s_defined': True, 'name': '_ZNSt3__16locale3allE', 'storage_mapping_class': 'RO', 'type': 'OBJECT'}
682 …_defined': True, 'name': '_ZNSt3__16locale4noneE', 'storage_mapping_class': 'RO', 'type': 'OBJECT'}
683 …_defined': True, 'name': '_ZNSt3__16locale4timeE', 'storage_mapping_class': 'RO', 'type': 'OBJECT'}
855 {'import_export': 'EXP', 'is_defined': True, 'name': '_ZSt7nothrow', 'storage_mapping_class': 'RO',…
953 …s_defined': True, 'name': '_ZTSNSt3__15ctypeIcEE', 'storage_mapping_class': 'RO', 'type': 'OBJECT'}
954 …s_defined': True, 'name': '_ZTSNSt3__15ctypeIwEE', 'storage_mapping_class': 'RO', 'type': 'OBJECT'}
963 …s_defined': True, 'name': '_ZTSNSt3__18ios_baseE', 'storage_mapping_class': 'RO', 'type': 'OBJECT'}
[all …]
H A Dpowerpc64-ibm-aix.libcxxabi.v1.stable.exceptions.nonew.abilist279 …_defined': True, 'name': '_ZNSt3__110adopt_lockE', 'storage_mapping_class': 'RO', 'type': 'OBJECT'}
292 …_defined': True, 'name': '_ZNSt3__110defer_lockE', 'storage_mapping_class': 'RO', 'type': 'OBJECT'}
322 …defined': True, 'name': '_ZNSt3__111try_to_lockE', 'storage_mapping_class': 'RO', 'type': 'OBJECT'}
681 …s_defined': True, 'name': '_ZNSt3__16locale3allE', 'storage_mapping_class': 'RO', 'type': 'OBJECT'}
682 …_defined': True, 'name': '_ZNSt3__16locale4noneE', 'storage_mapping_class': 'RO', 'type': 'OBJECT'}
683 …_defined': True, 'name': '_ZNSt3__16locale4timeE', 'storage_mapping_class': 'RO', 'type': 'OBJECT'}
855 {'import_export': 'EXP', 'is_defined': True, 'name': '_ZSt7nothrow', 'storage_mapping_class': 'RO',…
953 …s_defined': True, 'name': '_ZTSNSt3__15ctypeIcEE', 'storage_mapping_class': 'RO', 'type': 'OBJECT'}
954 …s_defined': True, 'name': '_ZTSNSt3__15ctypeIwEE', 'storage_mapping_class': 'RO', 'type': 'OBJECT'}
963 …s_defined': True, 'name': '_ZTSNSt3__18ios_baseE', 'storage_mapping_class': 'RO', 'type': 'OBJECT'}
[all …]
/llvm-project-15.0.7/llvm/test/Instrumentation/DataFlowSanitizer/
H A Dselect.ll17 ; TRACK_CF: %[[#RO:]] = or i[[#SBITS]] %[[#R+2]], %[[#R+3]]
19 ; TRACK_CF: store i[[#SBITS]] %[[#RO]], ptr @__dfsan_retval_tls, align [[ALIGN]]
39 ; TRACK_CF: %[[#RO:]] = or i[[#SBITS]] %[[#R+1]], %[[#R]]
41 ; TRACK_CF: store i[[#SBITS]] %[[#RO]], ptr @__dfsan_retval_tls, align [[ALIGN]]
61 ; TRACK_CF: %[[#RO:]] = or i[[#SBITS]] %[[#R+2]], %[[#R+3]]
63 ; TRACK_CF: store i[[#SBITS]] %[[#RO]], ptr @__dfsan_retval_tls, align [[ALIGN]]
70 ; NO_TRACK_CF: %[[#RO:]] = or i[[#SBITS]] %[[#R+1]], %[[#R]]
72 ; NO_TRACK_CF: store i[[#SBITS]] %[[#RO]], ptr @__dfsan_retval_tls, align [[ALIGN]]
H A Dorigin_abilist.ll33 ; CHECK: [[RO:%.*]] = select i1 {{.*}}, i32 [[BO]], i32 [[AO]]
34 ; CHECK: store i32 [[RO]], i32* @__dfsan_retval_origin_tls, align 4
139 ; CHECK: [[RO:%.*]] = load i32, i32* %originreturn, align 4
141 ; CHECK: store i32 [[RO]], i32* @__dfsan_retval_origin_tls, align 4
186 ; CHECK: [[RO:%.*]] = load i32, i32* %originreturn, align 4
188 ; CHECK: store i32 [[RO]], i32* @__dfsan_retval_origin_tls, align 4
204 ; CHECK: [[RO:%.*]] = load i32, i32* %originreturn, align 4
206 ; CHECK: store i32 [[RO]], i32* @__dfsan_retval_origin_tls, align 4
248 ; CHECK-NEXT: [[RO:%.*]] = load i32, i32* %originreturn, align 4
250 ; CHECK-NEXT: store i32 [[RO]], i32* @__dfsan_retval_origin_tls, align 4
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Daix-constant-align.ll20 ; CHECK: .csect .rodata.8[RO],3
28 ; CHECK: .csect .rodata[RO],2
33 ; CHECK: .csect NOT_PI[RO],3
H A Daix-xcoff-mergeable-str.ll29 ; CHECK: .csect .rodata.str2.2[RO],2
36 ; CHECK-NEXT: .csect .rodata.str4.4[RO],2
43 ; CHECK-NEXT: .csect .rodata.str1.1[RO],2
H A Daix-lower-constant-pool-index.ll48 ; 32SMALL-ASM: .csect .rodata[RO],2
57 ; 32LARGE-ASM: .csect .rodata[RO],2
67 ; 64SMALL-ASM: .csect .rodata[RO],2
76 ; 64LARGE-ASM: .csect .rodata[RO],2
H A Daix-xcoff-data-sections.ll67 ; CHECK-NEXT: .csect const_ivar[RO],2
68 ; CHECK-NEXT: .globl const_ivar[RO]
73 ; CHECK-NEXT: .csect .rodata.str1.1L...str[RO],2
78 ; CHECK32-NEXT: .vbyte 4, .rodata.str1.1L...str[RO]
82 ; CHECK64-NEXT: .vbyte 8, .rodata.str1.1L...str[RO]
93 ; CHECKOBJ: 00000038 (idx: 7) const_ivar[RO]:
96 ; CHECKOBJ-NEXT: 0000003c (idx: 9) .rodata.str1.1L...str[RO]:
H A Daix-lower-jump-table.ll105 ; 32SMALL-ASM: .csect .rodata[RO],2
132 ; 32LARGE-ASM: .csect .rodata[RO],2
158 ; 64SMALL-ASM: .csect .rodata[RO],2
185 ; 64LARGE-ASM: .csect .rodata[RO],2
201 ; FUNC-ASM: .csect .rodata.jmp..jump_table[RO],2
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DCFIInstrInserter.cpp371 CSRSavedLocation RO = it->second; in insertCFIInstrs() local
372 if (!RO.Reg && RO.Offset) { in insertCFIInstrs()
374 MCCFIInstruction::createOffset(nullptr, Reg, *RO.Offset)); in insertCFIInstrs()
375 } else if (RO.Reg && !RO.Offset) { in insertCFIInstrs()
377 MCCFIInstruction::createRegister(nullptr, Reg, *RO.Reg)); in insertCFIInstrs()
/llvm-project-15.0.7/llvm/test/Transforms/ObjCARC/
H A Drle-s2l.ll60 ; CHECK-NEXT: call void @use_pointer(i8* %x) [[RO:#[0-9]+]]
77 ; CHECK-NEXT: call void @use_pointer(i8* %x) [[RO]]
138 ; CHECK: attributes [[RO]] = { readonly }
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonEarlyIfConv.cpp820 const MachineOperand &RO = PN->getOperand(i), &BO = PN->getOperand(i+1); in updatePhiNodes() local
822 SR = RO.getReg(), SSR = RO.getSubReg(); in updatePhiNodes()
824 TR = RO.getReg(), TSR = RO.getSubReg(); in updatePhiNodes()
826 FR = RO.getReg(), FSR = RO.getSubReg(); in updatePhiNodes()

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