Lines Matching refs:RO
1317 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
1320 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
1322 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
1329 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
1333 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
1335 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
1351 class LogicNOR<string opstr, RegisterOperand RO>:
1352 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
1354 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
1360 RegisterOperand RO, InstrItinClass itin,
1363 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
1365 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> {
1369 class shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin,
1371 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
1373 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR,
1377 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
1378 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
1385 class LoadMemory<string opstr, DAGOperand RO, DAGOperand MO,
1389 InstSE<(outs RO:$rt), (ins MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
1390 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
1397 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
1399 LoadMemory<opstr, RO, mem, OpNode, Itin, Addr>;
1401 class StoreMemory<string opstr, DAGOperand RO, DAGOperand MO,
1404 InstSE<(outs), (ins RO:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
1405 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
1411 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
1414 StoreMemory<opstr, RO, MO, OpNode, Itin, Addr>;
1418 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
1420 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
1422 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
1428 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
1430 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
1431 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
1474 RegisterOperand RO> :
1475 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
1477 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], II_BCC,
1486 class CBranchLikely<string opstr, DAGOperand opnd, RegisterOperand RO> :
1487 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
1497 RegisterOperand RO> :
1498 InstSE<(outs), (ins RO:$rs, opnd:$offset),
1500 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], II_BCCZ,
1509 class CBranchZeroLikely<string opstr, DAGOperand opnd, RegisterOperand RO> :
1510 InstSE<(outs), (ins RO:$rs, opnd:$offset),
1520 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
1521 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
1523 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
1527 RegisterOperand RO>:
1528 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
1530 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
1561 class JumpFR<string opstr, RegisterOperand RO,
1563 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], II_JR,
1567 class IndirectBranch<string opstr, RegisterOperand RO> : JumpFR<opstr, RO> {
1580 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
1581 Register RetReg, RegisterOperand ResRO = RO>:
1582 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], II_JALR>,
1587 class JumpLinkReg<string opstr, RegisterOperand RO>:
1588 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
1594 RegisterOperand RO> :
1595 InstSE<(outs), (ins RO:$rs, opnd:$offset),
1608 class TailCallReg<Instruction JumpInst, RegisterOperand RO> :
1609 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], II_JR>,
1610 PseudoInstExpansion<(JumpInst RO:$rs)> {
1648 class DEI_FT<string opstr, RegisterOperand RO,
1650 InstSE<(outs RO:$rt), (ins),
1667 class TEQ_FT<string opstr, RegisterOperand RO, Operand ImmOp,
1669 InstSE<(outs), (ins RO:$rs, RO:$rt, ImmOp:$code_),
1672 class TEQI_FT<string opstr, RegisterOperand RO,
1674 InstSE<(outs), (ins RO:$rs, simm16:$imm16),
1679 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
1681 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
1715 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
1717 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
1727 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
1728 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO,
1740 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
1741 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO,
1748 class EffectiveAddress<string opstr, RegisterOperand RO> :
1749 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
1750 [(set RO:$rt, addr:$addr)], II_ADDIU, FrmI,
1758 class CountLeading0<string opstr, RegisterOperand RO,
1760 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
1761 [(set RO:$rd, (ctlz RO:$rs))], itin, FrmR, opstr>;
1763 class CountLeading1<string opstr, RegisterOperand RO,
1765 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
1766 [(set RO:$rd, (ctlz (not RO:$rs)))], itin, FrmR, opstr>;
1769 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO,
1771 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
1772 [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr>;
1775 class SubwordSwap<string opstr, RegisterOperand RO,
1777 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [], itin,
1783 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
1784 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd, uimm8:$sel),
1788 class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
1791 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, SizeOpnd:$size),
1793 [(set RO:$rt, (Op RO:$rs, PosImm:$pos, SizeImm:$size))], II_EXT,
1797 class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
1799 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, SizeOpnd:$size, RO:$src),
1801 [(set RO:$rt, (null_frag RO:$rs, PosImm:$pos, SizeImm:$size,
1802 RO:$src))],
1846 class LLBase<string opstr, RegisterOperand RO, DAGOperand MO = mem> :
1847 InstSE<(outs RO:$rt), (ins MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
1853 class SCBase<string opstr, RegisterOperand RO> :
1854 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
1861 class MFC3OP<string asmstr, RegisterOperand RO, RegisterOperand RD,
1863 InstSE<(outs RO:$rt), (ins RD:$rd, uimm3:$sel),
1868 class MTC3OP<string asmstr, RegisterOperand RO, RegisterOperand RD,
1870 InstSE<(outs RO:$rd), (ins RD:$rt, uimm3:$sel),
2281 class PseudoIndirectBranchBase<Instruction JumpInst, RegisterOperand RO> :
2282 MipsPseudo<(outs), (ins RO:$rs), [(brind RO:$rs)],
2284 PseudoInstExpansion<(JumpInst RO:$rs)> {
2302 class PseudoReturnBase<RegisterOperand RO> : MipsPseudo<(outs), (ins RO:$rs),
2471 class JR_HB_DESC<RegisterOperand RO> :
2472 InstSE<(outs), (ins), "", [], II_JR_HB, FrmJ>, JR_HB_DESC_BASE<"jr.hb", RO> {
2481 class JALR_HB_DESC<RegisterOperand RO> :
2483 RO> {
2663 RegisterOperand RO = GPR32Opnd,
2666 (Opcode RO:$rs,
2667 RO:$rt,
2670 (Opcode RO:$rs,
2671 RO:$rs,
2920 class LoadImmediate32<string instr_asm, Operand Od, RegisterOperand RO> :
2921 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
2926 RegisterOperand RO> :
2927 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
2931 class LoadAddressFromImm32<string instr_asm, Operand Od, RegisterOperand RO> :
2932 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
2941 class NORIMM_DESC_BASE<RegisterOperand RO, DAGOperand Imm> :
2942 MipsAsmPseudoInst<(outs RO:$rs), (ins RO:$rt, Imm:$imm),