Lines Matching refs:RO

203 class CompactBranchMM<string opstr, DAGOperand opnd, RegisterOperand RO> :
204   InstSE<(outs), (ins RO:$rs, opnd:$offset),
213 class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
215   InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),
217          [(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
226 class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
228   InstSE<(outs), (ins RO:$rt, MemOpnd:$addr),
230          [(OpNode RO:$rt, addrimm12:$addr)], Itin, FrmI> {
263 class LLBaseMM<string opstr, RegisterOperand RO> :
264   InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
270 class LLEBaseMM<string opstr, RegisterOperand RO> :
271   InstSE<(outs RO:$rt), (ins mem_simm9:$addr),
278 class SCBaseMM<string opstr, RegisterOperand RO> :
279   InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr),
286 class SCEBaseMM<string opstr, RegisterOperand RO> :
287   InstSE<(outs RO:$dst), (ins RO:$rt, mem_simm9:$addr),
295 class LoadMM<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
297   InstSE<(outs RO:$rt), (ins MO:$addr),
299          [(set RO:$rt, (OpNode addrimm12:$addr))], Itin, FrmI, opstr> {
305 class ArithRMM16<string opstr, RegisterOperand RO, bit isComm = 0,
308   MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, RO:$rt),
310                   [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
314 class AndImmMM16<string opstr, RegisterOperand RO,
316   MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, uimm4_andi:$imm),
319 class LogicRMM16<string opstr, RegisterOperand RO,
322   MicroMipsInst16<(outs RO:$dst), (ins RO:$rs, RO:$rt),
324          [(set RO:$dst, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
329 class NotMM16<string opstr, RegisterOperand RO> :
330   MicroMipsInst16<(outs RO:$rt), (ins RO:$rs),
332          [(set RO:$rt, (not RO:$rs))], II_NOT, FrmR>;
334 class ShiftIMM16<string opstr, Operand ImmOpnd, RegisterOperand RO,
336   MicroMipsInst16<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
339 class LoadMM16<string opstr, DAGOperand RO,
341   MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$addr),
356 class LoadSPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
358   MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$offset),
365 class StoreSPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
367   MicroMipsInst16<(outs), (ins RO:$rt, MemOpnd:$offset),
373 class LoadGPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
375   MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$offset),
382 class AddImmUR2<string opstr, RegisterOperand RO> :
383   MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, simm3_lsa2:$imm),
389 class AddImmUS5<string opstr, RegisterOperand RO> :
390   MicroMipsInst16<(outs RO:$dst), (ins RO:$rd, simm4:$imm),
395 class AddImmUR1SP<string opstr, RegisterOperand RO> :
396   MicroMipsInst16<(outs RO:$rd), (ins uimm6_lsl2:$imm),
403 class MoveFromHILOMM<string opstr, RegisterOperand RO, Register UseReg> :
404       MicroMipsInst16<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"),
411 class MoveMM16<string opstr, RegisterOperand RO>
412     :  MicroMipsInst16<(outs RO:$rd), (ins RO:$rs),
418 class LoadImmMM16<string opstr, Operand Od, RegisterOperand RO> :
419   MicroMipsInst16<(outs RO:$rd), (ins Od:$imm),
425 class JumpLinkRegMM16<string opstr, RegisterOperand RO> :
426   MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
427            [(MipsJmpLink RO:$rs)], II_JALR, FrmR> {
435 class JumpRegMM16<string opstr, RegisterOperand RO> :
436   MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
454 class JumpLinkRegSMM16<string opstr, RegisterOperand RO> :
455   MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
463 class JumpRegCMM16<string opstr, RegisterOperand RO> :
464   MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
478 class CBranchZeroMM<string opstr, DAGOperand opnd, RegisterOperand RO> :
479   MicroMipsInst16<(outs), (ins RO:$rs, opnd:$offset),
495   class JumpLinkRegMM<string opstr, RegisterOperand RO>:
496     InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
500                                   RegisterOperand RO> :
501     InstSE<(outs), (ins RO:$rs, opnd:$offset),
505 class LoadWordIndexedScaledMM<string opstr, RegisterOperand RO> :
506   InstSE<(outs RO:$rd), (ins PtrRC:$base, PtrRC:$index),
514 class AddImmUPC<string opstr, RegisterOperand RO> :
515   InstSE<(outs RO:$rs), (ins simm23_lsl2:$imm),