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Searched refs:RID (Results 1 – 19 of 19) sorted by relevance

/llvm-project-15.0.7/clang-tools-extra/pseudo/lib/grammar/
H A DGrammar.cpp37 const Rule &Grammar::lookupRule(RuleID RID) const { in lookupRule()
38 assert(RID < T->Rules.size()); in lookupRule()
39 return T->Rules[RID]; in lookupRule()
62 std::string Grammar::mangleRule(RuleID RID) const { in mangleRule()
63 const auto &R = lookupRule(RID); in mangleRule()
79 std::string Grammar::dumpRule(RuleID RID) const { in dumpRule()
82 const Rule &R = T->Rules[RID]; in dumpRule()
98 for (RuleID RID = Range.Start; RID < Range.End; ++RID) in dumpRules() local
99 Result.append(dumpRule(RID)).push_back('\n'); in dumpRules()
110 for (RuleID RID = 0; RID < T->Rules.size(); ++RID) in dump() local
[all …]
H A DLRGraph.cpp78 for (RuleID RID = RRange.Start; RID < RRange.End; ++RID) { in closure() local
79 Item NewItem = Item::start(RID, G); in closure()
140 const auto &Rule = G.lookupRule(RID); in dump()
236 for (RuleID RID = RRange.Start; RID < RRange.End; ++RID) { in buildLR0() local
237 auto StartState = std::vector<Item>{Item::start(RID, G)}; in buildLR0()
242 const Rule &StartRule = G.lookupRule(RID); in buildLR0()
H A DGrammarBNF.cpp330 for (RuleID RID = 0; RID + 1u < T.Rules.size(); ++RID) { in diagnoseGrammar() local
331 if (T.Rules[RID] == T.Rules[RID + 1]) in diagnoseGrammar()
333 llvm::formatv("Duplicate rule: `{0}`", G.dumpRule(RID))); in diagnoseGrammar()
/llvm-project-15.0.7/clang-tools-extra/pseudo/include/clang-pseudo/grammar/
H A DLRGraph.h54 I.RID = ID; in start()
60 I.RID = ID; in sentinel()
64 RuleID rule() const { return RID; } in rule()
70 return G.lookupRule(RID).Sequence[DotPos]; in next()
83 return DotPos == I.DotPos && RID == I.RID;
86 return std::tie(RID, DotPos) < std::tie(I.RID, I.DotPos);
89 return llvm::hash_combine(I.RID, I.DotPos); in hash_value()
93 RuleID RID = 0;
H A DGrammar.h159 const Rule &lookupRule(RuleID RID) const;
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dllvm.r600.tex.ll3 ;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNNN
4 ;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNNN
5 ;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNNN
6 ;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNNN
7 ;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:UUNN
8 ;CHECK: TEX_SAMPLE_C T{{[0-9]+\.XYZW, T[0-9]+\.XYZZ}} RID:0 SID:0 CT:NNNN
9 ;CHECK: TEX_SAMPLE_C T{{[0-9]+\.XYZW, T[0-9]+\.XYZZ}} RID:0 SID:0 CT:NNNN
10 ;CHECK: TEX_SAMPLE_C T{{[0-9]+\.XYZW, T[0-9]+\.XYZZ}} RID:0 SID:0 CT:UUNN
11 ;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYYW}} RID:0 SID:0 CT:NNUN
12 ;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNUN
[all …]
/llvm-project-15.0.7/clang-tools-extra/pseudo/gen/
H A DMain.cpp97 for (clang::pseudo::RuleID RID = 0; RID < G.table().Rules.size(); ++RID) in main() local
98 Out.os() << llvm::formatv("RULE({0}, {1})\n", G.mangleRule(RID), RID); in main()
/llvm-project-15.0.7/clang-tools-extra/pseudo/lib/
H A DGLR.cpp423 bool canReduce(const Rule &R, RuleID RID, in canReduce() argument
427 if (auto Guard = Lang.Guards.lookup(RID)) in canReduce()
448 if (!canReduce(Rule, RID, TempSequence)) in pop()
471 for (RuleID RID : in popPending() local
475 pop((*Heads)[NextPopHead], RID, Rule); in popPending()
560 llvm::Optional<RuleID> RID; in popAndPushTrivial() local
562 if (RID.has_value()) in popAndPushTrivial()
564 RID = R; in popAndPushTrivial()
566 if (!RID) in popAndPushTrivial()
568 const auto &Rule = Lang.G.lookupRule(*RID); in popAndPushTrivial()
[all …]
/llvm-project-15.0.7/clang-tools-extra/clang-doc/
H A DBitcodeWriter.cpp242 void ClangDocBitcodeWriter::AbbreviationMap::add(RecordId RID, in add() argument
244 assert(RecordIdNameMap[RID] && "Unknown RecordId."); in add()
245 assert(Abbrevs.find(RID) == Abbrevs.end() && "Abbreviation already added."); in add()
246 Abbrevs[RID] = AbbrevID; in add()
249 unsigned ClangDocBitcodeWriter::AbbreviationMap::get(RecordId RID) const { in get()
250 assert(RecordIdNameMap[RID] && "Unknown RecordId."); in get()
251 assert(Abbrevs.find(RID) != Abbrevs.end() && "Unknown abbreviation."); in get()
252 return Abbrevs.lookup(RID); in get()
393 for (RecordId RID : RIDs) { in emitBlockInfo() local
394 emitRecordID(RID); in emitBlockInfo()
[all …]
H A DBitcodeWriter.h170 void add(RecordId RID, unsigned AbbrevID);
171 unsigned get(RecordId RID) const;
/llvm-project-15.0.7/clang-tools-extra/pseudo/include/clang-pseudo/
H A DForest.h154 ForestNode &createSequence(SymbolID SID, RuleID RID, in createSequence() argument
159 ForestNode::sequenceData(RID, Elements), Elements); in createSequence()
/llvm-project-15.0.7/llvm/lib/Target/DirectX/DXILWriter/
H A DDXILValueEnumerator.cpp227 auto RID = OM.lookup(RU->getUser()).first; in predictValueUseListOrderImpl() local
235 if (OM.isGlobalValue(LID) && OM.isGlobalValue(RID)) { in predictValueUseListOrderImpl()
236 if (LID == RID) in predictValueUseListOrderImpl()
238 return LID < RID; in predictValueUseListOrderImpl()
242 if (LID < RID) { in predictValueUseListOrderImpl()
243 if (RID <= ID) in predictValueUseListOrderImpl()
248 if (RID < LID) { in predictValueUseListOrderImpl()
/llvm-project-15.0.7/llvm/lib/Bitcode/Writer/
H A DValueEnumerator.cpp188 auto RID = OM.lookup(RU->getUser()).first; in predictValueUseListOrderImpl() local
191 if (LID < RID) { in predictValueUseListOrderImpl()
192 if (RID <= ID) in predictValueUseListOrderImpl()
197 if (RID < LID) { in predictValueUseListOrderImpl()
/llvm-project-15.0.7/bolt/lib/Rewrite/
H A DBoltDiff.cpp696 RewriteInstanceDiff RID(*this, RI2); in compare() local
/llvm-project-15.0.7/llvm/lib/IR/
H A DAsmWriter.cpp202 auto RID = OM.lookup(RU->getUser()); in predictValueUseListOrder() local
205 if (LID < RID) { in predictValueUseListOrder()
207 if (RID <= ID) in predictValueUseListOrder()
211 if (RID < LID) { in predictValueUseListOrder()
/llvm-project-15.0.7/llvm/docs/PDB/
H A DDbiStream.rst443 **Token / RID Map** - ``DbgStreamArray[6]``. The layout of this stream is not
/llvm-project-15.0.7/clang/lib/Sema/
H A DSemaObjCProperty.cpp2027 if (const ObjCInterfaceDecl *RID = ID->isObjCRequiresPropertyDefs()) in DiagnoseUnimplementedAccessor() local
2028 S.Diag(RID->getLocation(), diag::note_suppressed_class_declare); in DiagnoseUnimplementedAccessor()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600Instructions.td926 "RID:$RESOURCE_ID SID:$SAMPLER_ID "
/llvm-project-15.0.7/llvm/lib/Analysis/
H A DScalarEvolution.cpp641 unsigned LID = LV->getValueID(), RID = RV->getValueID(); in CompareValueComplexity() local
642 if (LID != RID) in CompareValueComplexity()
643 return (int)LID - (int)RID; in CompareValueComplexity()