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/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dselectcc-03.ll10 ; CHECK-NEXT: sllg [[REG]], [[REG]], 32
24 ; CHECK-NEXT: sllg [[REG]], [[REG]], 32
37 ; CHECK-NEXT: sllg [[REG]], [[REG]], 32
51 ; CHECK-NEXT: sllg [[REG]], [[REG]], 32
64 ; CHECK-NEXT: sllg [[REG]], [[REG]], 35
77 ; CHECK-NEXT: sllg [[REG]], [[REG]], 34
90 ; CHECK-NEXT: sllg [[REG]], [[REG]], 32
103 ; CHECK-NEXT: sllg [[REG]], [[REG]], 32
116 ; CHECK-NEXT: sllg [[REG]], [[REG]], 34
128 ; CHECK-NEXT: sllg [[REG]], [[REG]], 35
[all …]
H A Dsetcc-04.ll8 ; CHECK: ipm [[REG:%r[0-5]]]
20 ; CHECK: ipm [[REG:%r[0-5]]]
33 ; CHECK: ipm [[REG:%r[0-5]]]
45 ; CHECK: ipm [[REG:%r[0-5]]]
58 ; CHECK: ipm [[REG:%r[0-5]]]
70 ; CHECK: ipm [[REG:%r[0-5]]]
82 ; CHECK: ipm [[REG:%r[0-5]]]
94 ; CHECK: ipm [[REG:%r[0-5]]]
106 ; CHECK: ipm [[REG:%r[0-5]]]
118 ; CHECK: ipm [[REG:%r[0-5]]]
[all …]
H A Dvec-div-01.ll9 ; CHECK: vlvgp [[REG:%v[0-9]+]],
10 ; CHECK-DAG: vlvgb [[REG]], {{%r[0-9]+}}, 0
11 ; CHECK-DAG: vlvgb [[REG]], {{%r[0-9]+}}, 1
12 ; CHECK-DAG: vlvgb [[REG]], {{%r[0-9]+}}, 2
13 ; CHECK-DAG: vlvgb [[REG]], {{%r[0-9]+}}, 3
14 ; CHECK-DAG: vlvgb [[REG]], {{%r[0-9]+}}, 4
15 ; CHECK-DAG: vlvgb [[REG]], {{%r[0-9]+}}, 5
16 ; CHECK-DAG: vlvgb [[REG]], {{%r[0-9]+}}, 6
17 ; CHECK-DAG: vlvgb [[REG]], {{%r[0-9]+}}, 8
32 ; CHECK: vlvgp [[REG:%v[0-9]+]],
[all …]
H A Dsetcc-03.ll8 ; CHECK: ipm [[REG:%r[0-5]]]
9 ; CHECK-NEXT: afi [[REG]], -268435456
10 ; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 33
20 ; CHECK: ipm [[REG:%r[0-5]]]
31 ; CHECK: ipm [[REG:%r[0-5]]]
32 ; CHECK-NEXT: afi [[REG]], -536870912
43 ; CHECK: ipm [[REG:%r[0-5]]]
54 ; CHECK: ipm [[REG:%r[0-5]]]
55 ; CHECK-NEXT: xilf [[REG]], 4294967295
66 ; CHECK: ipm [[REG:%r[0-5]]]
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dbig-endian-neon-extend.ll6 ; CHECK-NEXT: vrev16.8 [[REG]], [[REG]]
21 ; CHECK-NEXT: vrev32.16 [[REG]], [[REG]]
36 ; CHECK-NEXT: vrev16.8 [[REG]], [[REG]]
39 ; CHECK-NEXT: vrev64.32 [[REG]], [[REG]]
51 ; CHECK-NEXT: vrev32.16 [[REG]], [[REG]]
53 ; CHECK-NEXT: vrev64.32 [[REG]], [[REG]]
65 ; CHECK-NEXT: vrev16.8 [[REG]], [[REG]]
68 ; CHECK-NEXT: vrev32.16 [[REG]], [[REG]]
82 ; CHECK-NEXT: vrev32.8 [[REG]], [[REG]]
97 ; CHECK-NEXT: vrev32.8 [[REG]], [[REG]]
[all …]
H A Darm-position-independence.ll35 ; ARM_RW_ABS: ldr r0, [r[[REG]]]
39 ; ARM_RW_SB: ldr r0, [r9, r[[REG]]]
46 ; THUMB2_RW_ABS: ldr r0, [r[[REG]]]
56 ; THUMB1_RW_ABS: ldr r0, [r[[REG]]]
96 ; THUMB2_RW_ABS: str r0, [r[[REG]]]
106 ; THUMB1_RW_ABS: str r0, [r[[REG]]]
160 ; THUMB2_RO_PC: ldr r0, [r[[REG]]]
174 ; THUMB1_RO_PC: ldr r0, [r[[REG]]]
207 ; ARM_RW_SB: add r0, r9, r[[REG]]
226 ; THUMB1_RW_SB: adds r[[REG]], r[[REG_SB]], r[[REG]]
[all …]
H A Dbig-endian-neon-trunc-store.ll5 ; CHECK: vmovn.i64 [[REG:d[0-9]+]]
6 ; CHECK: vrev32.16 [[REG]], [[REG]]
7 ; CHECK: vuzp.16 [[REG]], [[REG2:d[0-9]+]]
8 ; CHECK: vrev32.16 [[REG]], [[REG2]]
17 ; CHECK: vmovn.i32 [[REG:d[0-9]+]]
18 ; CHECK: vrev16.8 [[REG]], [[REG]]
19 ; CHECK: vuzp.8 [[REG]], [[REG2:d[0-9]+]]
20 ; CHECK: vrev32.8 [[REG]], [[REG2]]
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dasm-mismatched-types.ll12 ; CHECK: # REG: %r8d
19 ; CHECK: # REG: %r8d
26 ; CHECK: # REG: %r9w
33 ; CHECK: # REG: %bpl
40 ; CHECK: # REG: %r15w
47 ; CHECK: # REG: %r12b
54 ; CHECK: # REG: %cl
61 ; CHECK: # REG: %rbp
68 ; CHECK: # REG: %rbp
75 ; CHECK: # REG: %r13
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dfloat-to-int.ll18 ; CHECK: stfd [[REG]],
24 ; CHECK-VSX: stfd [[REG]],
30 ; CHECK-P9: stfd [[REG]],
41 ; CHECK: stfd [[REG]],
53 ; CHECK-P9: stfd [[REG]],
64 ; CHECK: stfd [[REG]],
76 ; CHECK-P9: stfd [[REG]],
87 ; CHECK: stfd [[REG]],
110 ; CHECK: stfiwx [[REG]],
127 ; CHECK: stfiwx [[REG]],
[all …]
H A Dvsx.ll24 ; CHECK-REG-LABEL: test1:
27 ; CHECK-REG-NEXT: blr
51 ; CHECK-REG-LABEL: test2:
54 ; CHECK-REG-NEXT: blr
78 ; CHECK-REG-LABEL: test3:
81 ; CHECK-REG-NEXT: blr
105 ; CHECK-REG-LABEL: test4:
108 ; CHECK-REG-NEXT: blr
135 ; CHECK-REG-NEXT: blr
163 ; CHECK-REG-NEXT: blr
[all …]
H A Di64-to-float.ll17 ; CHECK: lfd [[REG:[0-9]+]],
18 ; CHECK: fcfids 1, [[REG]]
23 ; CHECK-VSX: lfd [[REG:[0-9]+]],
24 ; CHECK-VSX: fcfids 1, [[REG]]
29 ; CHECK-P9: lfd [[REG:[0-9]+]],
41 ; CHECK: lfd [[REG:[0-9]+]],
42 ; CHECK: fcfid 1, [[REG]]
65 ; CHECK: lfd [[REG:[0-9]+]],
66 ; CHECK: fcfidus 1, [[REG]]
89 ; CHECK: lfd [[REG:[0-9]+]],
[all …]
H A Di32-to-float.ll14 ; CHECK: extsw [[REG:[0-9]+]], 3
15 ; CHECK: std [[REG]],
31 ; CHECK-A2: fcfids 1, [[REG]]
37 ; CHECK-VSX: fcfids 1, [[REG]]
47 ; CHECK: extsw [[REG:[0-9]+]], 3
48 ; CHECK: std [[REG]],
56 ; CHECK-PWR6: fcfid 1, [[REG]]
62 ; CHECK-A2: fcfid 1, [[REG]]
80 ; CHECK-A2: fcfidus 1, [[REG]]
86 ; CHECK-VSX: fcfidus 1, [[REG]]
[all …]
H A Dfusion-load-store.ll15 ; CHECK: SU([[SU2]]): STD %[[REG:[0-9]+]]:g8rc, 24
16 ; CHECK: SU([[SU3]]): STD %[[REG]]:g8rc, 16
17 ; CHECK: SU([[SU4]]): STD %[[REG]]:g8rc, 8
18 ; CHECK: SU([[SU5]]): STD %[[REG]]:g8rc, 32
24 ; CHECK: SU([[SU1]]): STD renamable $x[[REG]], 8
74 ; CHECK: SU([[SU3]]): STD %[[REG]]:g8rc, -8
75 ; CHECK: SU([[SU4]]): STD %[[REG]]:g8rc, -16
76 ; CHECK: SU([[SU5]]): STD %[[REG]]:g8rc, -32
190 ; CHECK: SU([[SU3]]): STD %[[REG]]:g8rc, 16
191 ; CHECK: SU([[SU4]]): STD %[[REG]]:g8rc, 8
[all …]
H A Dfsel.ll37 ; CHECK-FM: fneg [[REG:[0-9]+]], 1
38 ; CHECK-FM: fsel 1, [[REG]], 3, 2
43 ; CHECK-FM-VSX: fsel 1, [[REG]], 3, 2
81 ; CHECK-FM: fsub [[REG:[0-9]+]], 2, 1
82 ; CHECK-FM: fsel 1, [[REG]], 1, 2
87 ; CHECK-FM-VSX: fsel 1, [[REG]], 1, 2
102 ; CHECK-FM: fsub [[REG:[0-9]+]], 1, 2
103 ; CHECK-FM: fsel 1, [[REG]], 1, 2
108 ; CHECK-FM-VSX: fsel 1, [[REG]], 1, 2
124 ; CHECK-FM: fsel 1, [[REG]], 3, 4
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dfast-isel-runtime-libcall.ll9 ; LARGE: ldr [[REG]], [[[REG]], _fmodf@GOTPAGEOFF]
10 ; LARGE-NEXT: blr [[REG]]
20 ; LARGE: ldr [[REG]], [[[REG]], _fmod@GOTPAGEOFF]
21 ; LARGE-NEXT: blr [[REG]]
31 ; LARGE: ldr [[REG]], [[[REG]], _sinf@GOTPAGEOFF]
32 ; LARGE-NEXT: blr [[REG]]
42 ; LARGE: ldr [[REG]], [[[REG]], _sin@GOTPAGEOFF]
53 ; LARGE: ldr [[REG]], [[[REG]], _cosf@GOTPAGEOFF]
64 ; LARGE: ldr [[REG]], [[[REG]], _cos@GOTPAGEOFF]
75 ; LARGE: ldr [[REG]], [[[REG]], _powf@GOTPAGEOFF]
[all …]
H A Dtagged-globals-pic.ll26 ; CHECK-PIC: adrp [[REG:x[0-9]+]], :got:global
42 ; CHECK-GLOBALISEL: add [[REG]], [[REG]], :lo12:global
43 ; CHECK-GLOBALISEL: ldr w0, [[[REG]]]
47 ; CHECK-PIC: adrp [[REG:x[0-9]+]], :got:global
48 ; CHECK-PIC: ldr [[REG]], [[[REG]], :got_lo12:global]
49 ; CHECK-PIC: ldr w0, [[[REG]]]
65 ; CHECK-GLOBALISEL: add [[REG]], [[REG]], :lo12:global
66 ; CHECK-GLOBALISEL: str wzr, [[[REG]]]
71 ; CHECK-PIC: ldr [[REG]], [[[REG]], :got_lo12:global]
72 ; CHECK-PIC: str wzr, [[[REG]]]
[all …]
H A Dtagged-globals-static.ll18 ; CHECK-STATIC: adrp [[REG:x[0-9]+]], :pg_hi21_nc:global
19 ; CHECK-STATIC: movk [[REG]], #:prel_g3:global+4294967296
20 ; CHECK-STATIC: add x0, [[REG]], :lo12:global
29 ; CHECK-SELECTIONDAGISEL: ldr w0, [[[REG]], :lo12:global]
35 ; CHECK-GLOBALISEL: add [[REG]], [[REG]], :lo12:global
36 ; CHECK-GLOBALISEL: ldr w0, [[[REG]]]
46 ; CHECK-SELECTIONDAGISEL: str wzr, [[[REG]], :lo12:global]
52 ; CHECK-GLOBALISEL: add [[REG]], [[REG]], :lo12:global
53 ; CHECK-GLOBALISEL: str wzr, [[[REG]]]
62 ; CHECK-STATIC: adrp [[REG:x[0-9]+]], func
[all …]
H A Darm64-fast-isel-icmp.ll7 ; CHECK-NEXT: cset [[REG:w[0-9]+]], eq
8 ; CHECK-NEXT: and w0, [[REG]], #0x1
18 ; CHECK-NEXT: cset [[REG:w[0-9]+]], eq
19 ; CHECK-NEXT: and w0, [[REG]], #0x1
29 ; CHECK-NEXT: cset [[REG:w[0-9]+]], eq
30 ; CHECK-NEXT: and w0, [[REG]], #0x1
41 ; CHECK-NEXT: and w0, [[REG]], #0x1
72 ; CHECK-NEXT: and w0, [[REG]], #0x1
83 ; CHECK-NEXT: and w0, [[REG]], #0x1
94 ; CHECK-NEXT: and w0, [[REG]], #0x1
[all …]
H A Dfast-isel-int-ext3.ll10 ; CHECK: ldurb [[REG:w[0-9]+]], [x0, #-8]
11 ; CHECK: uxtb w0, [[REG]]
22 ; CHECK: uxth w0, [[REG]]
33 ; CHECK: ubfx x0, x[[REG]], #0, #8
44 ; CHECK: ubfx x0, x[[REG]], #0, #16
55 ; CHECK: ubfx x0, x[[REG]], #0, #32
66 ; CHECK: sxtb w0, [[REG]]
77 ; CHECK: sxth w0, [[REG]]
88 ; CHECK: sxtb x0, [[REG]]
99 ; CHECK: sxth x0, [[REG]]
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dr600.global_atomics.ll7 ; EG: MEM_RAT ATOMIC_ADD [[REG:T[0-9]+]]
8 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z
17 ; EG: MEM_RAT ATOMIC_ADD [[REG:T[0-9]+]]
18 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z
29 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z
40 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z
51 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z
60 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z
70 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z
80 ; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z
[all …]
H A Dimmv216.ll123 ; GFX9: buffer_store_dword [[REG]]
148 ; GFX9: buffer_store_dword [[REG]]
173 ; GFX9: buffer_store_dword [[REG]]
198 ; GFX9: buffer_store_dword [[REG]]
223 ; GFX9: buffer_store_dword [[REG]]
249 ; GFX9: buffer_store_dword [[REG]]
274 ; GFX9: buffer_store_dword [[REG]]
299 ; GFX9: buffer_store_dword [[REG]]
477 ; VI: buffer_store_dword [[REG]]
498 ; VI: buffer_store_dword [[REG]]
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/
H A Dinlineasm-mve.ll25 ; CHECK: add [[REG:r1*[0, 2, 4, 6, 8]]], [[REG]], #1
26 ; CHECK: add [[REG:r1*[0, 2, 4, 6, 8]]], [[REG]], #2
27 ; CHECK: add [[REG:r1*[0, 2, 4, 6, 8]]], [[REG]], #3
28 ; CHECK: add [[REG:r1*[0, 2, 4, 6, 8]]], [[REG]], #4
39 ; CHECK: add [[REG:r1*[1, 3, 5, 7, 9]]], [[REG]], #1
40 ; CHECK: add [[REG:r1*[1, 3, 5, 7, 9]]], [[REG]], #2
41 ; CHECK: add [[REG:r1*[1, 3, 5, 7, 9]]], [[REG]], #3
42 ; CHECK: add [[REG:r1*[1, 3, 5, 7, 9]]], [[REG]], #4
/llvm-project-15.0.7/lld/test/MachO/
H A Dtlv.s10 # RUN: FileCheck %s --check-prefix=REG-TLVP
16 # RUN: FileCheck %s --check-prefix=REG-TLVP
26 # RUN: FileCheck %s --check-prefix=REG-TBSS-TLVP
36 # REG: <_main>:
37 # REG-NEXT: leaq {{.*}}(%rip), %rax ## {{.*}} <_foo>
38 # REG-NEXT: leaq {{.*}}(%rip), %rax ## {{.*}} <_bar>
39 # REG-NEXT: retq
47 # REG-TLVP: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
48 # REG-TLVP-NEXT: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
49 # REG-TLVP-NEXT: 00 00 00 00 00 00 00 00 08 00 00 00 00 00 00 00
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/RISCV/
H A Dreg-usage.ll25 ; CHECK-SCALAR: LV(REG): Found max usage: 2 item
28 ; CHECK-SCALAR-NEXT: LV(REG): Found invariant usage: 1 item
30 ; CHECK-LMUL1: LV(REG): Found max usage: 2 item
32 ; CHECK-LMUL1-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 2 registers
33 ; CHECK-LMUL1-NEXT: LV(REG): Found invariant usage: 1 item
35 ; CHECK-LMUL2: LV(REG): Found max usage: 2 item
38 ; CHECK-LMUL2-NEXT: LV(REG): Found invariant usage: 1 item
40 ; CHECK-LMUL4: LV(REG): Found max usage: 2 item
43 ; CHECK-LMUL4-NEXT: LV(REG): Found invariant usage: 1 item
45 ; CHECK-LMUL8: LV(REG): Found max usage: 2 item
[all …]
/llvm-project-15.0.7/lldb/source/Plugins/Process/FreeBSDKernel/
H A DRegisterContextFreeBSDKernel_x86_64.cpp62 #define REG(x) \ in ReadRegister() macro
67 REG(r15); in ReadRegister()
68 REG(r14); in ReadRegister()
69 REG(r13); in ReadRegister()
70 REG(r12); in ReadRegister()
71 REG(rbp); in ReadRegister()
72 REG(rsp); in ReadRegister()
73 REG(rbx); in ReadRegister()
74 REG(rip); in ReadRegister()
76 #undef REG in ReadRegister()

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