immv216.ll - OpenGrok cross reference for /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/immv216.ll

Lines Matching refs:REG
9 ; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x80008000 ; encoding
10 ; GCN: buffer_store_{{dword|b32}} [[REG]]
17 ; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0 ; encoding
18 ; GCN: buffer_store_{{dword|b32}} [[REG]]
25 ; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x80008000 ; encoding
26 ; GCN: buffer_store_{{dword|b32}} [[REG]]
33 ; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x38003800 ; encoding
34 ; GCN: buffer_store_{{dword|b32}} [[REG]]
41 ; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0xb800b800 ; encoding
42 ; GCN: buffer_store_{{dword|b32}} [[REG]]
49 ; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x3c003c00 ; encoding
50 ; GCN: buffer_store_{{dword|b32}} [[REG]]
57 ; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0xbc00bc00 ; encoding
58 ; GCN: buffer_store_{{dword|b32}} [[REG]]
65 ; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x40004000 ; encoding
66 ; GCN: buffer_store_{{dword|b32}} [[REG]]
73 ; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0xc000c000 ; encoding
74 ; GCN: buffer_store_{{dword|b32}} [[REG]]
81 ; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x44004400 ; encoding
82 ; GCN: buffer_store_{{dword|b32}} [[REG]]
89 ; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0xc400c400 ; encoding
90 ; GCN: buffer_store_{{dword|b32}} [[REG]]
97 ; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x31183118 ; encoding
98 ; GCN: buffer_store_{{dword|b32}} [[REG]]
105 ; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0xb118b118 ; encoding
106 ; GCN: buffer_store_{{dword|b32}} [[REG]]
113 ; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x6c006c00
114 ; GCN: buffer_store_{{dword|b32}} [[REG]]
122 ; GFX9: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], 0 ; encoding
123 ; GFX9: buffer_store_dword [[REG]]
143 ; GFX10: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], 0.5 op_sel_hi:[1,0] ; encoding: [0x00,0x40,0x0f,0xc…
144 ; GFX10: buffer_store_{{dword|b32}} [[REG]]
147 ; GFX9: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], 0.5 op_sel_hi:[1,0] ; encoding: [0x00,0x40,0x8f,0xd3…
148 ; GFX9: buffer_store_dword [[REG]]
168 ; GFX10: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], -0.5 op_sel_hi:[1,0] ; encoding: [0x00,0x40,0x0f,0x…
169 ; GFX10: buffer_store_{{dword|b32}} [[REG]]
172 ; GFX9: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], -0.5 op_sel_hi:[1,0] ; encoding: [0x00,0x40,0x8f,0xd…
173 ; GFX9: buffer_store_dword [[REG]]
193 ; GFX10: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], 1.0 op_sel_hi:[1,0] ; encoding:
194 ; GFX10: buffer_store_{{dword|b32}} [[REG]]
197 ; GFX9: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], 1.0 op_sel_hi:[1,0] ; encoding
198 ; GFX9: buffer_store_dword [[REG]]
218 ; GFX10: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], -1.0 op_sel_hi:[1,0] ; encoding
219 ; GFX10: buffer_store_{{dword|b32}} [[REG]]
222 ; GFX9: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], -1.0 op_sel_hi:[1,0] ; encoding
223 ; GFX9: buffer_store_dword [[REG]]
244 ; GFX10: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], 2.0 op_sel_hi:[1,0] ; encoding
245 ; GFX10: buffer_store_{{dword|b32}} [[REG]]
248 ; GFX9: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], 2.0 op_sel_hi:[1,0] ; encoding
249 ; GFX9: buffer_store_dword [[REG]]
269 ; GFX10: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], -2.0 op_sel_hi:[1,0] ; encoding
270 ; GFX10: buffer_store_{{dword|b32}} [[REG]]
273 ; GFX9: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], -2.0 op_sel_hi:[1,0] ; encoding
274 ; GFX9: buffer_store_dword [[REG]]
294 ; GFX10: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], 4.0 op_sel_hi:[1,0] ; encoding
295 ; GFX10: buffer_store_{{dword|b32}} [[REG]]
298 ; GFX9: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], 4.0 op_sel_hi:[1,0] ; encoding
299 ; GFX9: buffer_store_dword [[REG]]
319 ; GFX10: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], -4.0 op_sel_hi:[1,0] ; encoding
320 ; GFX10: buffer_store_{{dword|b32}} [[REG]]
323 ; GFX9: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], -4.0 op_sel_hi:[1,0] ; encoding
324 ; GFX9: buffer_store_dword [[REG]]
344 ; GFX10: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], 0.5
345 ; GFX10: buffer_store_{{dword|b32}} [[REG]]
348 ; GFX9: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], 0.5
349 ; GFX9: buffer_store_dword [[REG]]
370 ; GFX9: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], [[K]] op_sel_hi:[1,0] ; encoding: [0x00,0x40,0x8f,0x…
371 ; GFX9: buffer_store_dword [[REG]]
390 ; GFX10: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], 1 op_sel_hi:[1,0] ; encoding
391 ; GFX10: buffer_store_{{dword|b32}} [[REG]]
394 ; GFX9: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], 1 op_sel_hi:[1,0] ; encoding
395 ; GFX9: buffer_store_dword [[REG]]
415 ; GFX10: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], 2 op_sel_hi:[1,0] ; encoding
416 ; GFX10: buffer_store_{{dword|b32}} [[REG]]
419 ; GFX9: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], 2 op_sel_hi:[1,0] ; encoding
420 ; GFX9: buffer_store_dword [[REG]]
441 ; GFX10: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], 16 op_sel_hi:[1,0] ; encoding
442 ; GFX10: buffer_store_{{dword|b32}} [[REG]]
445 ; GFX9: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], 16 op_sel_hi:[1,0] ; encoding
446 ; GFX9: buffer_store_dword [[REG]]
467 ; GFX10: v_mov_b32_e32 [[REG:v[0-9]+]], [[VAL]]
468 ; GFX10: buffer_store_{{dword|b32}} [[REG]]
471 ; GFX9: v_mov_b32_e32 [[REG:v[0-9]+]], [[VAL]]
472 ; GFX9: buffer_store_dword [[REG]]
476 ; VI: v_mov_b32_e32 [[REG:v[0-9]+]], [[ADD]]
477 ; VI: buffer_store_dword [[REG]]
488 ; GFX10: v_mov_b32_e32 [[REG:v[0-9]+]], [[VAL]]
489 ; GFX10: buffer_store_{{dword|b32}} [[REG]]
492 ; GFX9: v_mov_b32_e32 [[REG:v[0-9]+]], [[VAL]]
493 ; GFX9: buffer_store_dword [[REG]]
497 ; VI: v_mov_b32_e32 [[REG:v[0-9]+]], [[ADD]]
498 ; VI: buffer_store_dword [[REG]]
509 ; GFX10: v_mov_b32_e32 [[REG:v[0-9]+]], [[VAL]]
510 ; GFX10: buffer_store_{{dword|b32}} [[REG]]
513 ; GFX9: v_mov_b32_e32 [[REG:v[0-9]+]], [[VAL]]
514 ; GFX9: buffer_store_dword [[REG]]
519 ; VI: v_mov_b32_e32 [[REG:v[0-9]+]], [[ADD]]
520 ; VI: buffer_store_dword [[REG]]
531 ; GFX10: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], 63
532 ; GFX10: buffer_store_{{dword|b32}} [[REG]]
535 ; GFX9: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], 63
536 ; GFX9: buffer_store_dword [[REG]]
556 ; GFX10: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], 64
557 ; GFX10: buffer_store_{{dword|b32}} [[REG]]
560 ; GFX9: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], 64
561 ; GFX9: buffer_store_dword [[REG]]