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Searched refs:RC2 (Results 1 – 12 of 12) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonPatternsV65.td43 multiclass vgathermhq<RegisterClass RC1, RegisterClass RC2> {
48 RC2:$Vq, IntRegs:$Rt, ModRegs:$Mu,
54 multiclass vgathermwq<RegisterClass RC1, RegisterClass RC2> {
59 RC2:$Vq, IntRegs:$Rt, ModRegs:$Mu,
65 multiclass vgathermhwq<RegisterClass RC1, RegisterClass RC2> {
70 RC2:$Vq, IntRegs:$Rt, ModRegs:$Mu,
H A DHexagonGenInsert.cpp340 const BitTracker::RegisterCell &RC1 = CM.lookup(VR1), &RC2 = CM.lookup(VR2); in operator ()() local
341 uint16_t W1 = RC1.width(), W2 = RC2.width(); in operator ()()
343 const BitTracker::BitValue &V1 = RC1[i], &V2 = RC2[i]; in operator ()()
358 const BitTracker::RegisterCell &RC2 = CM.lookup(VR2); in operator ()() local
359 uint16_t W1 = RC1.width(), W2 = RC2.width(); in operator ()()
373 const BitTracker::BitValue &V1 = RC1[Bit1], V2 = RC2[Bit2]; in operator ()()
H A DHexagonBitSimplify.cpp232 const BitTracker::RegisterCell &RC2, uint16_t B2, uint16_t W);
343 uint16_t B1, const BitTracker::RegisterCell &RC2, uint16_t B2, in isEqual() argument
350 if (RC2[B2+i].Type == BitTracker::BitValue::Ref && RC2[B2+i].RefI.Reg == 0) in isEqual()
352 if (RC1[B1+i] != RC2[B2+i]) in isEqual()
/llvm-project-15.0.7/llvm/test/Transforms/Attributor/
H A Dnorecurse.ll266 ; IS__TUNIT____-NEXT: [[RC2:%.*]] = call i1 @rec(i1 [[C]])
267 ; IS__TUNIT____-NEXT: ret i1 [[RC2]]
277 ; IS__CGSCC____-NEXT: [[RC2:%.*]] = call noundef i1 @rec(i1 [[C]])
278 ; IS__CGSCC____-NEXT: ret i1 [[RC2]]
/llvm-project-15.0.7/llvm/unittests/Analysis/
H A DLazyCallGraphTest.cpp2053 LazyCallGraph::RefSCC &RC2 = *I++; in TEST() local
2148 LazyCallGraph::RefSCC &RC2 = *I++; in TEST() local
2172 EXPECT_EQ(&RC2, &*I++); in TEST()
2210 LazyCallGraph::RefSCC *RC2 = &*I++; in TEST() local
2211 EXPECT_EQ(RC2, ORC); in TEST()
2251 LazyCallGraph::RefSCC *RC2 = &*I++; in TEST() local
2252 EXPECT_EQ(RC2, ORC); in TEST()
2628 LazyCallGraph::RefSCC *RC2 = &*I++; in TEST() local
2629 EXPECT_EQ(RC2, ORC); in TEST()
2728 LazyCallGraph::RefSCC *RC2 = &*I++; in TEST() local
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsSEFrameLowering.cpp318 const TargetRegisterClass *RC2 = in expandBuildPairF64() local
323 int FI = MF.getInfo<MipsFunctionInfo>()->getMoveF64ViaSpillFI(MF, RC2); in expandBuildPairF64()
330 TII.loadRegFromStack(MBB, I, DstReg, FI, RC2, &RegInfo, 0); in expandBuildPairF64()
385 const TargetRegisterClass *RC2 = &Mips::GPR32RegClass; in expandExtractElementF64() local
391 TII.loadRegFromStack(MBB, I, DstReg, FI, RC2, &RegInfo, Offset); in expandExtractElementF64()
/llvm-project-15.0.7/clang/test/Driver/
H A Dhip-phases.hip108 // RUN: | FileCheck -check-prefixes=RDC2,RC2 %s
122 // RC2-DAG: [[P9:[0-9]+]]: offload, "device-[[T]] (amdgcn-amd-amdhsa:[[ARCH1]])" {[[P6]]}, ir
130 // RC2-DAG: [[P16:[0-9]+]]: offload, "device-[[T]] (amdgcn-amd-amdhsa:[[ARCH2]])" {[[P13]]}, ir
132 // RC2-DAG: [[P0:[0-9]+]]: input, "{{.*}}hip-phases.hip", [[T:hip]], (host-[[T]])
133 // RC2-DAG: [[P1:[0-9]+]]: preprocessor, {[[P0]]}, [[T]]-cpp-output, (host-[[T]])
134 // RC2-DAG: [[P2:[0-9]+]]: compiler, {[[P1]]}, ir, (host-[[T]])
135 // RC2-DAG: [[P19:[0-9]+]]: backend, {[[P2]]}, assembler, (host-[[T]])
136 // RC2-DAG: [[P20:[0-9]+]]: assembler, {[[P19]]}, object, (host-[[T]])
141 // RC2-DAG: [[P23:[0-9]+]]: clang-offload-bundler, {[[P9]], [[P16]], [[P20]]}, object, (host-[[T]])
/llvm-project-15.0.7/llvm/docs/
H A DReleaseProcess.rst42 fixed between RC1 and RC2, but not so much at the end of it.
79 * On the pre-release, you should change ``-rc 1`` to ``-final``. On RC2,
H A DHowToReleaseLLVM.rst333 #. *Before RC2* Patches should be limited to bug fixes or backend specific
/llvm-project-15.0.7/llvm/utils/TableGen/
H A DCodeGenRegisters.cpp2199 CodeGenRegisterClass *RC2 = &*I; in inferCommonSubClass() local
2200 if (RC1 == RC2) in inferCommonSubClass()
2205 const CodeGenRegister::Vec &Memb2 = RC2->getMembers(); in inferCommonSubClass()
2218 if (RC2->RSI.hasStricterSpillThan(RC1->RSI)) in inferCommonSubClass()
2219 std::swap(RC1, RC2); in inferCommonSubClass()
2222 RC1->getName() + "_and_" + RC2->getName()); in inferCommonSubClass()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp866 auto RC2 = SrcReg2 != 0 ? MRI.getRegClass(SrcReg2) : nullptr; in PPCEmitCmp() local
888 if (RC2 && isVSSRCRegClass(RC2)) in PPCEmitCmp()
906 } else if (isVSFRCRegClass(RC1) || (RC2 && isVSFRCRegClass(RC2))) { in PPCEmitCmp()
/llvm-project-15.0.7/clang/lib/Sema/
H A DSemaOverload.cpp9929 Expr *RC2 = Cand2.Function->getTrailingRequiresClause(); in isBetterOverloadCandidate() local
9930 if (RC1 && RC2) { in isBetterOverloadCandidate()
9932 if (S.IsAtLeastAsConstrained(Cand1.Function, {RC1}, Cand2.Function, {RC2}, in isBetterOverloadCandidate()
9934 S.IsAtLeastAsConstrained(Cand2.Function, {RC2}, Cand1.Function, {RC1}, in isBetterOverloadCandidate()
9939 } else if (RC1 || RC2) { in isBetterOverloadCandidate()