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/llvm-project-15.0.7/flang/unittests/Evaluate/
H A Dfolding.cpp42 using R4 = Type<TypeCategory::Real, 4>; in TestHostRuntimeSubnormalFlushing() typedef
43 if constexpr (std::is_same_v<host::HostType<R4>, float>) { in TestHostRuntimeSubnormalFlushing()
57 DynamicType r4{R4{}.GetType()}; in TestHostRuntimeSubnormalFlushing()
61 const Scalar<R4> x1{Scalar<R4>::Word{0x00400000}}; in TestHostRuntimeSubnormalFlushing()
62 Scalar<R4> y1Flushing{CallHostRt<R4>(*callable, flushingContext, x1)}; in TestHostRuntimeSubnormalFlushing()
63 Scalar<R4> y1NoFlushing{CallHostRt<R4>(*callable, noFlushingContext, x1)}; in TestHostRuntimeSubnormalFlushing()
69 std::abs(host::CastFortranToHost<R4>(y1Flushing) + 88.) > 2); in TestHostRuntimeSubnormalFlushing()
71 std::abs(host::CastFortranToHost<R4>(y1NoFlushing) + 88.) < 2); in TestHostRuntimeSubnormalFlushing()
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/Windows/
H A Dvla.ll16 ; CHECK-SMALL-CODE: adds [[R4:r[0-9]+]], #7
17 ; CHECK-SMALL-CODE: bic [[R4]], [[R4]], #4
18 ; CHECK-SMALL-CODE: lsrs r4, [[R4]], #2
22 ; CHECK-LARGE-CODE: adds [[R4:r[0-9]+]], #7
23 ; CHECK-LARGE-CODE: bic [[R4]], [[R4]], #4
24 ; CHECK-LARGE-CODE: lsrs r4, [[R4]], #2
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dldm-stm-base-materialization.ll18 ; CHECK-NEXT: stm [[NSB]], {[[R1]], [[R2]], [[R3]], [[R4]], [[R5]], [[R6]]}
38 ; CHECK-NEXT: ldm [[NLB]], {[[R1:[rl0-9]+]], [[R2:[rl0-9]+]], [[R3:[rl0-9]+]], [[R4:[rl0-9]+]]}
39 ; CHECK-NEXT: stm [[NSB]], {[[R1]], [[R2]], [[R3]], [[R4]]}
57 ; CHECK-NEXT: ldm [[NLB]]!, {[[R1:[rl0-9]+]], [[R2:[rl0-9]+]], [[R3:[rl0-9]+]], [[R4:[rl0-9]+]]}
58 ; CHECK-NEXT: stm [[NSB]]!, {[[R1]], [[R2]], [[R3]], [[R4]]}
59 ; CHECK-NEXT: ldm [[NLB]], {[[R1:[rl0-9]+]], [[R2:[rl0-9]+]], [[R3:[rl0-9]+]], [[R4:[rl0-9]+]]}
60 ; CHECK-NEXT: stm [[NSB]], {[[R1]], [[R2]], [[R3]], [[R4]]}
78 ; CHECK-NEXT: ldm [[NLB]]!, {[[R1:[rl0-9]+]], [[R2:[rl0-9]+]], [[R3:[rl0-9]+]], [[R4:[rl0-9]+]]}
79 ; CHECK-NEXT: stm [[NSB]]!, {[[R1]], [[R2]], [[R3]], [[R4]]}
80 ; CHECK-NEXT: ldm [[NLB]], {[[R1:[rl0-9]+]], [[R2:[rl0-9]+]], [[R3:[rl0-9]+]], [[R4:[rl0-9]+]], [[R…
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb/
H A Dldm-stm-base-materialization-thumb2.ll18 ; CHECK-NEXT: stm{{(\.w)?}} [[SB]], {[[R1]], [[R2]], [[R3]], [[R4]], [[R5]], [[R6]]}
38 ; CHECK-NEXT: ldm{{(\.w)?}} [[NLB]], {[[R1:[rl0-9]+]], [[R2:[rl0-9]+]], [[R3:[rl0-9]+]], [[R4:[rl0-…
39 ; CHECK-NEXT: stm{{(\.w)?}} [[SB]], {[[R1]], [[R2]], [[R3]], [[R4]]}
57 ; CHECK-NEXT: ldm{{(\.w)?}} [[NLB]]!, {[[R1:[rl0-9]+]], [[R2:[rl0-9]+]], [[R3:[rl0-9]+]], [[R4:[rl0…
58 ; CHECK-NEXT: stm{{(\.w)?}} [[SB]]!, {[[R1]], [[R2]], [[R3]], [[R4]]}
59 ; CHECK-NEXT: ldm{{(\.w)?}} [[NLB]], {[[R1:[rl0-9]+]], [[R2:[rl0-9]+]], [[R3:[rl0-9]+]], [[R4:[rl0-…
60 ; CHECK-NEXT: stm{{(\.w)?}} [[SB]], {[[R1]], [[R2]], [[R3]], [[R4]]}
78 ; CHECK-NEXT: ldm{{(\.w)?}} [[NLB]]!, {[[R1:[rl0-9]+]], [[R2:[rl0-9]+]], [[R3:[rl0-9]+]], [[R4:[rl0…
79 ; CHECK-NEXT: stm{{(\.w)?}} [[SB]]!, {[[R1]], [[R2]], [[R3]], [[R4]]}
80 ; CHECK-NEXT: ldm{{(\.w)?}} [[NLB]], {[[R1:[rl0-9]+]], [[R2:[rl0-9]+]], [[R3:[rl0-9]+]], [[R4:[rl0-…
[all …]
H A Dldm-stm-base-materialization.ll39 ; CHECK-NEXT: ldm r[[NLB]]!, {r[[R1:[0-9]]], r[[R2:[0-9]]], r[[R3:[0-9]]], r[[R4:[0-9]]]}
40 ; CHECK-NEXT: stm r[[NSB]]!, {r[[R1]], r[[R2]], r[[R3]], r[[R4]]}
58 ; CHECK-NEXT: ldm r[[NLB]]!, {r[[R1:[0-9]]], r[[R2:[0-9]]], r[[R3:[0-9]]], r[[R4:[0-9]]]}
59 ; CHECK-NEXT: stm r[[NSB]]!, {r[[R1]], r[[R2]], r[[R3]], r[[R4]]}
60 ; CHECK-NEXT: ldm r[[NLB]]!, {r[[R1:[0-9]]], r[[R2:[0-9]]], r[[R3:[0-9]]], r[[R4:[0-9]]]}
61 ; CHECK-NEXT: stm r[[NSB]]!, {r[[R1]], r[[R2]], r[[R3]], r[[R4]]}
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/msa/
H A D3r_splat.ll26 ; MIPS32-DAG: splat.b [[R4:\$w[0-9]+]], [[R3]][$4]
27 ; MIPS32-DAG: st.b [[R4]], 0([[R2]])
47 ; MIPS32-DAG: splat.h [[R4:\$w[0-9]+]], [[R3]][$4]
48 ; MIPS32-DAG: st.h [[R4]], 0([[R2]])
68 ; MIPS32-DAG: splat.w [[R4:\$w[0-9]+]], [[R3]][$4]
69 ; MIPS32-DAG: st.w [[R4]], 0([[R2]])
89 ; MIPS32-DAG: splat.d [[R4:\$w[0-9]+]], [[R3]][$4]
90 ; MIPS32-DAG: st.d [[R4]], 0([[R2]])
104 ; MIPS32-DAG: splat.d [[R4:\$w[0-9]+]], [[R3]][$4]
105 ; MIPS32-DAG: st.d [[R4]], 0([[R2]])
[all …]
H A Dbmzi_bmnzi.ll24 ; CHECK: ld.b [[R4:\$w[0-9]+]], 0([[R1]])
25 ; CHECK: move.v [[R5:\$w[0-9]+]], [[R4]]
28 ; CHECK: bmnzi.b [[R4]], [[R3]], 170
47 ; CHECK: ld.b [[R4:\$w[0-9]+]], 0([[R1]])
48 ; CHECK: move.v [[R5:\$w[0-9]+]], [[R4]]
52 ; CHECK: bmnzi.b [[R4]], [[R3]], 170
H A Dbitcast.ll52 ; BIGENDIAN: st.h [[R4]],
100 ; BIGENDIAN: st.w [[R4]],
125 ; BIGENDIAN: st.w [[R4]],
151 ; BIGENDIAN: st.d [[R4]],
177 ; BIGENDIAN: st.d [[R4]],
202 ; BIGENDIAN: st.b [[R4]],
274 ; BIGENDIAN: st.w [[R4]],
299 ; BIGENDIAN: st.w [[R4]],
324 ; BIGENDIAN: st.d [[R4]],
349 ; BIGENDIAN: st.d [[R4]],
[all …]
H A D3r-b.ll119 ; CHECK-DAG: binsl.b [[R4]], [[R5]], [[R6]]
120 ; CHECK-DAG: st.b [[R4]], 0(
147 ; CHECK-DAG: binsl.h [[R4]], [[R5]], [[R6]]
148 ; CHECK-DAG: st.h [[R4]], 0(
175 ; CHECK-DAG: binsl.w [[R4]], [[R5]], [[R6]]
176 ; CHECK-DAG: st.w [[R4]], 0(
204 ; CHECK-DAG: st.d [[R4]], 0(
232 ; CHECK-DAG: st.b [[R4]], 0(
260 ; CHECK-DAG: st.h [[R4]], 0(
288 ; CHECK-DAG: st.w [[R4]], 0(
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dcttz-v.ll12 ; MIPS32-DAG: addiu $[[R4:[0-9]+]], $zero, 32
13 ; MIPS32-DAG: subu $2, $[[R4]], $[[R3]]
19 ; MIPS32-DAG: subu $3, $[[R4]], $[[R8]]
26 ; MIPS64-DAG: addiu $[[R4:[0-9]+]], $zero, 32
27 ; MIPS64-DAG: subu $[[R5:[0-9]+]], $[[R4]], $[[R3]]
35 ; MIPS64-DAG: subu $[[R13:[0-9]+]], $[[R4]], $[[R12]]
H A D2010-07-20-Switch.ll27 ; PIC-O32: lw $[[R4:[0-9]+]], %lo($JTI0_0)($[[R2]])
28 ; PIC-O32: addu $[[R5:[0-9]+]], $[[R4:[0-9]+]]
36 ; STATIC-N64: daddiu $[[R4:[0-9]]], $[[R3]], %hi(.LJTI0_0)
37 ; STATIC-N64: dsll $[[R5:[0-9]]], $[[R4]], 16
38 ; STATIC-N64: daddu $[[R6:[0-9]]], $[[R0]], $[[R4]]
44 ; PIC-N64: ld $[[R4:[0-9]+]], %got_ofst(.LJTI0_0)($[[R2]])
45 ; PIC-N64: daddu $[[R5:[0-9]+]], $[[R4:[0-9]+]]
H A Dbswap.ll29 ; MIPS16-DAG: li $[[R4:[0-9]+]], 65280
30 ; MIPS16-DAG: and $[[R4]], $[[R0]]
31 ; MIPS16-DAG: or $[[R1]], $[[R4]]
64 ; MIPS16-DAG: li $[[R4:[0-9]+]], 65280
65 ; MIPS16-DAG: and $[[R0]], $[[R4]]
75 ; MIPS16-DAG: and $[[R0]], $[[R4]]
H A Dmips64-f128-call.ll36 ; CHECK: dsll $[[R4:[0-9]+]], $[[R3]], 16
37 ; CHECK: ldc1 $f0, %lo(gld1)($[[R4]])
38 ; CHECK: daddiu $[[R5:[0-9]]], $[[R4]], %lo(gld1)
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dshift128.ll11 ; CHECK-DAG: srd [[R4:[0-9]+]], 4, [[R1]]
13 ; CHECK-DAG: or 3, [[R5]], [[R4]]
25 ; CHECK-DAG: srad [[R4:[0-9]+]], 4, [[R1]]
29 ; CHECK-DAG: isellt 3, [[R5]], [[R4]]
40 ; CHECK-DAG: sld [[R4:[0-9]+]], 3, [[R1]]
42 ; CHECK-DAG: or 4, [[R5]], [[R4]]
/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430RegisterInfo.cpp42 MSP430::R4, MSP430::R5, MSP430::R6, MSP430::R7, in getCalleeSavedRegs()
52 MSP430::R4, MSP430::R5, MSP430::R6, MSP430::R7, in getCalleeSavedRegs()
90 Reserved.set(MSP430::R4); in getReservedRegs()
115 unsigned BasePtr = (TFI->hasFP(MF) ? MSP430::R4 : MSP430::SP); in eliminateFrameIndex()
159 return TFI->hasFP(MF) ? MSP430::R4 : MSP430::SP; in getFrameRegister()
H A DMSP430FrameLowering.cpp67 .addReg(MSP430::R4, RegState::Kill); in emitPrologue()
70 BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::R4) in emitPrologue()
75 MBBJ.addLiveIn(MSP430::R4); in emitPrologue()
134 BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::R4); in emitEpilogue()
156 TII.get(MSP430::MOV16rr), MSP430::SP).addReg(MSP430::R4); in emitEpilogue()
/llvm-project-15.0.7/llvm/test/CodeGen/SPARC/
H A Dblockaddr.ll37 ; abs64: sllx [[R3]], 32, [[R4:%[gilo][0-7]]]
48 ; v8pic32: add [[R3]], %lo([[BLK]]), %[[R4:[gilo][0-7]]]
50 ; v8pic32: ld [%[[R2]]+%[[R4]]], %o0
59 ; v9pic32: add [[R3]], %lo([[BLK]]), %[[R4:[gilo][0-7]]]
61 ; v9pic32: ldx [%[[R2]]+%[[R4]]], %o0
/llvm-project-15.0.7/compiler-rt/lib/builtins/hexagon/
H A Dfastmath2_dlib_asm.S61 #define expa R4
72 #define k R4
162 #define expa R4
173 #define k R4
263 #define expa R4
375 #define expo R4
461 #define maxnegl R4
H A Dfastmath2_ldlib_asm.S56 #define expa R4
62 #define k R4
155 #define expa R4
161 #define k R4
260 #define expa R4
H A Dfastmath_dlib_asm.S63 #define expa R4
79 #define k R4
198 #define expa R4
214 #define k R4
327 #define expa R4
339 #define k R4
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/cconv/
H A Darguments-float.ll67 ; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 20($sp)
69 ; O32-DAG: sw [[R4]], 28([[R2]])
73 ; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 28($sp)
75 ; O32-DAG: sw [[R4]], 36([[R2]])
79 ; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 36($sp)
81 ; O32-DAG: sw [[R4]], 44([[R2]])
85 ; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 44($sp)
87 ; O32-DAG: sw [[R4]], 52([[R2]])
93 ; O32-DAG: sw [[R4]], 60([[R2]])
98 ; O32-DAG: lw [[R4:\$[0-9]+]], 60($sp)
[all …]
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCCallingConv.cpp37 PPC::R3, PPC::R4, PPC::R5, PPC::R6, in CC_PPC32_SVR4_Custom_AlignArgRegs()
62 PPC::R3, PPC::R4, PPC::R5, PPC::R6, in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
115 static const MCPhysReg LoRegList[] = { PPC::R4, PPC::R6, PPC::R8, PPC::R10 }; in CC_PPC32_SPE_CustomSplitFP64()
144 static const MCPhysReg LoRegList[] = { PPC::R4 }; in CC_PPC32_SPE_RetF64()
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFCallingConv.td22 CCIfType<[i64], CCAssignToReg<[ R1, R2, R3, R4, R5 ]>>,
38 [R1, R2, R3, R4, R5]>>,
41 CCIfType<[i64], CCAssignToRegWithShadow<[R1, R2, R3, R4, R5],
/llvm-project-15.0.7/llvm/lib/Target/XCore/
H A DXCoreRegisterInfo.td29 def R4 : Ri< 4, "r4">, DwarfRegNum<[4]>;
48 R4, R5, R6, R7, R8, R9, R10,
55 R4, R5, R6, R7, R8, R9, R10,
/llvm-project-15.0.7/llvm/test/TableGen/
H A DAsmPredicateCombining.td29 def R4 : Register<"r4">;
31 def Regs : RegisterClass<"Regs", [i32], 32, (add R0, R1, R2, R3, R4)>;
102 def : InstAlias<"alias5", (insn6 R4)> { let Predicates = [AsmPred1, AsmPred3]; }
103 // WRITER: // (insn6 R4)
104 // WRITER-NEXT: {AliasPatternCond::K_Reg, arch::R4},

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