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Searched refs:PREFETCH (Results 1 – 25 of 28) sorted by relevance

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/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dprefetch-02.ll2 ; RUN: -stop-after=loop-data-prefetch | FileCheck %s -check-prefix=FAR-PREFETCH
4 ; RUN: -stop-after=loop-data-prefetch | FileCheck %s -check-prefix=NEAR-PREFETCH
9 ; FAR-PREFETCH-LABEL: fun
10 ; FAR-PREFETCH-NOT: call void @llvm.prefetch
12 ; NEAR-PREFETCH-LABEL: fun
13 ; NEAR-PREFETCH: call void @llvm.prefetch
/llvm-project-15.0.7/compiler-rt/lib/scudo/standalone/
H A Dinternal_defs.h43 #define PREFETCH(X) __asm__("prefetchnta (%0)" : : "r"(X)) macro
45 #define PREFETCH(X) __builtin_prefetch(X) macro
H A Dquarantine.h284 PREFETCH(B->Batch[I]); in doRecycle()
287 PREFETCH(B->Batch[I + NumberOfPrefetch]); in doRecycle()
/llvm-project-15.0.7/compiler-rt/lib/sanitizer_common/
H A Dsanitizer_internal_defs.h225 # define PREFETCH(x) /* _mm_prefetch(x, _MM_HINT_NTA) */ (void)0 macro
241 # define PREFETCH(x) __asm__("prefetchnta (%0)" : : "r" (x)) macro
243 # define PREFETCH(x) __builtin_prefetch(x) macro
H A Dsanitizer_quarantine.h189 PREFETCH(b->batch[i]); in DoRecycle()
192 PREFETCH(b->batch[i + kPrefetch]); in DoRecycle()
H A Dsanitizer_allocator_local_cache.h169 PREFETCH(c->batch[c->count - 1]); in Allocate()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86IntrinsicsInfo.h24 GATHER, SCATTER, PREFETCH, RDSEED, RDRAND, RDPMC, RDTSC, XTEST, XGETBV, ADX, FPCLASSS, enumerator
111 X86_INTRINSIC_DATA(avx512_gatherpf_dpd_512, PREFETCH,
113 X86_INTRINSIC_DATA(avx512_gatherpf_dps_512, PREFETCH,
115 X86_INTRINSIC_DATA(avx512_gatherpf_qpd_512, PREFETCH,
117 X86_INTRINSIC_DATA(avx512_gatherpf_qps_512, PREFETCH,
295 X86_INTRINSIC_DATA(avx512_scatterpf_dpd_512, PREFETCH, X86::VSCATTERPF0DPDm,
297 X86_INTRINSIC_DATA(avx512_scatterpf_dps_512, PREFETCH, X86::VSCATTERPF0DPSm,
299 X86_INTRINSIC_DATA(avx512_scatterpf_qpd_512, PREFETCH, X86::VSCATTERPF0QPDm,
301 X86_INTRINSIC_DATA(avx512_scatterpf_qps_512, PREFETCH, X86::VSCATTERPF0QPSm,
H A DX86Instr3DNow.td94 def PREFETCH : I3DNow<0x0D, MRM0m, (outs), (ins i8mem:$addr),
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1146 PREFETCH, enumerator
H A DSelectionDAGNodes.h1390 case ISD::PREFETCH:
1498 N->getOpcode() == ISD::PREFETCH ||
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.h364 PREFETCH enumerator
H A DSystemZOperators.td428 def z_prefetch : SDNode<"SystemZISD::PREFETCH", SDT_ZPrefetch,
H A DSystemZISelLowering.cpp325 setOperationAction(ISD::PREFETCH, MVT::Other, Custom); in SystemZTargetLowering()
4433 return DAG.getMemIntrinsicNode(SystemZISD::PREFETCH, DL, in lowerPREFETCH()
5783 case ISD::PREFETCH: in LowerOperation()
6030 OPCODE(PREFETCH); in getTargetNodeName()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp81 case ISD::PREFETCH: return "Prefetch"; in getOperationName()
H A DSelectionDAG.cpp826 case ISD::PREFETCH: { in AddNodeIDCustom()
7621 Opcode == ISD::PREFETCH || in getMemIntrinsicNode()
H A DLegalizeDAG.cpp2753 case ISD::PREFETCH: in ExpandNode()
H A DLegalizeIntegerTypes.cpp1691 case ISD::PREFETCH: Res = PromoteIntOp_PREFETCH(N, OpNo); break; in PromoteIntegerOperand()
H A DSelectionDAGBuilder.cpp6847 ISD::PREFETCH, sdl, DAG.getVTList(MVT::Other), Ops, in visitIntrinsicCall()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h276 PREFETCH, enumerator
H A DAArch64ISelLowering.cpp707 setOperationAction(ISD::PREFETCH, MVT::Other, Custom); in AArch64TargetLowering()
2208 MAKE_CASE(AArch64ISD::PREFETCH) in getTargetNodeName()
3680 return DAG.getNode(AArch64ISD::PREFETCH, DL, MVT::Other, Op.getOperand(0), in LowerPREFETCH()
5493 case ISD::PREFETCH: in LowerOperation()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp874 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); in initActions()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1502 setOperationAction(ISD::PREFETCH, MVT::Other, Custom); in HexagonTargetLowering()
3234 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG); in LowerOperation()
H A DHexagonPatterns.td3230 // We need custom lowering of ISD::PREFETCH into HexagonISD::DCFETCH
3231 // because the SDNode ISD::PREFETCH has properties MayLoad and MayStore.
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td614 def prefetch : SDNode<"ISD::PREFETCH" , SDTPrefetch,
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp1383 setOperationAction(ISD::PREFETCH, MVT::Other, Custom); in ARMTargetLowering()
10353 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget); in LowerOperation()

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