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/llvm-project-15.0.7/llvm/test/CodeGen/NVPTX/
H A Df16-instructions.ll377 ; CHECK-NEXT: selp.u32 [[R:%r[0-9]+]], 1, 0, [[PRED]];
393 ; CHECK-NEXT: selp.u32 [[R:%r[0-9]+]], 1, 0, [[PRED]];
409 ; CHECK-NEXT: selp.u32 [[R:%r[0-9]+]], 1, 0, [[PRED]];
425 ; CHECK-NEXT: selp.u32 [[R:%r[0-9]+]], 1, 0, [[PRED]];
441 ; CHECK-NEXT: selp.u32 [[R:%r[0-9]+]], 1, 0, [[PRED]];
457 ; CHECK-NEXT: selp.u32 [[R:%r[0-9]+]], 1, 0, [[PRED]];
474 ; CHECK-NEXT: selp.u32 [[R:%r[0-9]+]], 1, 0, [[PRED]];
490 ; CHECK-NEXT: selp.u32 [[R:%r[0-9]+]], 1, 0, [[PRED]];
506 ; CHECK-NEXT: selp.u32 [[R:%r[0-9]+]], 1, 0, [[PRED]];
604 ; CHECK-NEXT: @[[PRED]] bra [[LABEL:\$L__BB.*]];
[all …]
H A Dlower-aggr-copies.ll43 ; PTX: setp.lt.u64 %p[[PRED:[0-9]+]], %rd[[COUNTER]], %rd
44 ; PTX: @%p[[PRED]] bra $L__BB[[LABEL]]
77 ; PTX: setp.lt.u64 %p[[PRED:[0-9]+]], %rd[[COUNTER]], %rd
78 ; PTX: @%p[[PRED]] bra $L__BB[[LABEL]]
136 ; PTX: setp.lt.u64 %p[[PRED:[0-9]+]], %rd[[COUNTER]], %rd
137 ; PTX: @%p[[PRED]] bra $L__BB[[LABEL]]
/llvm-project-15.0.7/llvm/test/Transforms/SimplifyCFG/
H A Dswitch_ub.ll68 ; CHECK-NEXT: br i1 [[COND:%.*]], label [[BB:%.*]], label [[PRED:%.*]]
79 … 1, [[DO_1]] ], [ 1, [[DO_2]] ], [ 1, [[DO_3]] ], [ 0, [[PRED]] ], [ 0, [[PRED]] ], [ 0, [[PRED]] ]
131 ; CHECK-NEXT: br i1 [[COND:%.*]], label [[BB:%.*]], label [[PRED:%.*]]
139 …= phi i32 [ [[R:%.*]], [[BB]] ], [ 1, [[DO_1]] ], [ 1, [[DO_2]] ], [ 1, [[DO_3]] ], [ 0, [[PRED]] ]
H A Dswitch_create-custom-dl.ll787 ; CHECK-NEXT: [[PRED:%.*]] = or i1 [[CMP1]], [[CMP2]]
788 ; CHECK-NEXT: br i1 [[PRED]], label [[IF:%.*]], label [[COMMON_RET:%.*]]
843 ; CHECK-NEXT: [[PRED:%.*]] = and i1 [[CMP1]], [[CMP2]]
844 ; CHECK-NEXT: br i1 [[PRED]], label [[IF:%.*]], label [[COMMON_RET:%.*]]
H A Dswitch_create.ll994 ; CHECK-NEXT: [[PRED:%.*]] = or i1 [[CMP1]], [[CMP2]]
995 ; CHECK-NEXT: br i1 [[PRED]], label [[IF:%.*]], label [[COMMON_RET:%.*]]
1050 ; CHECK-NEXT: [[PRED:%.*]] = and i1 [[CMP1]], [[CMP2]]
1051 ; CHECK-NEXT: br i1 [[PRED]], label [[IF:%.*]], label [[COMMON_RET:%.*]]
/llvm-project-15.0.7/llvm/test/Transforms/OpenMP/
H A Dfold_generic_main_thread.ll70 ; CHECK-DISABLED-NEXT: [[PRED:%.*]] = icmp eq i8 [[ISMAIN]], 1
71 ; CHECK-DISABLED-NEXT: br i1 [[PRED]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
98 ; CHECK-NEXT: [[PRED:%.*]] = icmp eq i8 [[ISMAIN]], 1
99 ; CHECK-NEXT: br i1 [[PRED]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
110 ; CHECK-DISABLED-NEXT: [[PRED:%.*]] = icmp eq i8 [[ISMAIN]], 1
111 ; CHECK-DISABLED-NEXT: br i1 [[PRED]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/AArch64/
H A Dsve-intrinsic-gatherscatter.ll14 …f64.p0nxv2f64(<vscale x 2 x double>* [[TMP2]], i32 1, <vscale x 2 x i1> [[PRED:%.*]], <vscale x 2 …
25 … x double> @llvm.aarch64.sve.ld1.gather.index.nxv2f64(<vscale x 2 x i1> [[PRED:%.*]], double* [[X:…
37 …f64.p0nxv2f64(<vscale x 2 x double>* [[TMP2]], i32 8, <vscale x 2 x i1> [[PRED:%.*]], <vscale x 2 …
53 … x 2 x double> [[VAL:%.*]], <vscale x 2 x double>* [[TMP2]], i32 1, <vscale x 2 x i1> [[PRED:%.*]])
64 …tter.index.nxv2f64(<vscale x 2 x double> [[VAL:%.*]], <vscale x 2 x i1> [[PRED:%.*]], double* [[X:…
76 … x 2 x double> [[VAL:%.*]], <vscale x 2 x double>* [[TMP2]], i32 8, <vscale x 2 x i1> [[PRED:%.*]])
/llvm-project-15.0.7/mlir/test/Dialect/SCF/
H A Dfor-loop-specialization.mlir28 // CHECK: [[PRED:%.*]] = arith.cmpi eq, [[MIN]], [[CST_1024]] : index
29 // CHECK: scf.if [[PRED]] {
H A Dbufferize.mlir4 // CHECK-SAME: %[[PRED:.*]]: i1,
9 // CHECK: %[[RESULT_MEMREF:.*]] = scf.if %[[PRED]] -> (memref<?xf32>) {
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/
H A Dpred-sched.ll4 ; CHECK: p[[PRED:[0-3]]] = tstbit
5 ; CHECK: if (p[[PRED]].new)
/llvm-project-15.0.7/mlir/test/Conversion/TosaToLinalg/
H A Dtosa-to-linalg.mlir1659 // CHECK: %[[PRED:.+]] = arith.cmpi slt, %[[Y0]], %[[XYMIN]]
1661 // CHECK: %[[PRED:.+]] = arith.cmpi slt, %[[YMAX]], %[[Y0]]
1664 // CHECK: %[[PRED:.+]] = arith.cmpi slt, %[[Y1]], %[[XYMIN]]
1666 // CHECK: %[[PRED:.+]] = arith.cmpi slt, %[[YMAX]], %[[Y1]]
1669 // CHECK: %[[PRED:.+]] = arith.cmpi slt, %[[X0]], %[[XYMIN]]
1671 // CHECK: %[[PRED:.+]] = arith.cmpi slt, %[[XMAX]], %[[X0]]
1676 // CHECK: %[[PRED:.+]] = arith.cmpi slt, %[[XMAX]], %[[X1]]
1809 // CHECK: %[[PRED:.+]] = arith.cmpi slt, %[[YMAX]], %[[Y0]]
1814 // CHECK: %[[PRED:.+]] = arith.cmpi slt, %[[YMAX]], %[[Y1]]
1819 // CHECK: %[[PRED:.+]] = arith.cmpi slt, %[[XMAX]], %[[X0]]
[all …]
/llvm-project-15.0.7/mlir/test/Dialect/Arithmetic/
H A Dbufferize.mlir87 // CHECK-SAME: %[[PRED:.*]]: i1,
92 // CHECK: %[[RET_MEMREF:.*]] = arith.select %[[PRED]], %[[TRUE_VAL_MEMREF]], %[[FALSE_VAL…
/llvm-project-15.0.7/llvm/test/Transforms/SCCP/
H A Dconditions-ranges-with-undef.ll174 ; CHECK-NEXT: br label [[PRED:%.*]]
176 ; CHECK-NEXT: br label [[PRED]]
227 ; CHECK-NEXT: br label [[PRED:%.*]]
229 ; CHECK-NEXT: br label [[PRED]]
/llvm-project-15.0.7/mlir/test/Dialect/Linalg/
H A Dconvert-elementwise-to-linalg.mlir64 // CHECK: ^bb0(%[[PRED:.*]]: i1, %[[TRUE_VAL:.*]]: i32, %[[FALSE_VAL:.*]]: i32, %{{.*}}: i32):
65 // CHECK: arith.select %[[PRED]], %[[TRUE_VAL]], %[[FALSE_VAL]] : i32
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/
H A Dvplan-sink-scalars-and-merge.ll47 ; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[PRED:%.+]]> = ir<%lv.b>
107 ; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[PRED:%.+]]> = ir<%lv.b>
121 ; CHECK-NEXT: REPLICATE ir<%add> = add vp<[[PRED]]>, ir<10>
186 ; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[PRED:%.+]]> = ir<%lv.b>
191 ; CHECK-NEXT: WIDEN ir<%add> = add vp<[[PRED]]>, ir<10>
348 ; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[PRED:%.+]]> = ir<%lv.b>
359 ; CHECK-NEXT: BLEND %p = ir<0>/vp<[[MASK3]]> vp<[[PRED]]>/vp<[[MASK2]]>
450 ; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[PRED:%.+]]> = ir<%lv.b>
461 ; CHECK-NEXT: BLEND %p = ir<0>/vp<[[MASK3]]> vp<[[PRED]]>/vp<[[MASK2]]>
853 ; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[PRED]]> = ir<%lv.a>
[all …]
H A Dfirst-order-recurrence-sink-replicate-region.ll137 ; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[PRED:%.+]]> = ir<%rem>
206 ; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[PRED:%.+]]> = ir<%rem>
212 ; CHECK-NEXT: WIDEN ir<%add> = add vp<[[PRED]]>, ir<%recur.next>
282 ; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[PRED:%.+]]> = ir<%lv>
288 ; CHECK-NEXT: WIDEN ir<%conv> = sext vp<[[PRED]]>
382 ; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[PRED:%.+]]> = ir<%rem>
396 ; CHECK-NEXT: REPLICATE ir<%rem.div> = sdiv ir<20>, vp<[[PRED]]>
H A Dvplan-printing.ll224 ; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[PRED:%.+]]> = ir<%tmp4>
234 ; CHECK-NEXT: BLEND %d = ir<0>/vp<[[NOT]]> vp<[[PRED]]>/ir<%cmp>
H A Dloop-form.ll1136 ; CHECK-NEXT: [[PRED:%.*]] = fcmp oeq float [[TMP12]], 0.000000e+00
1137 ; CHECK-NEXT: br i1 [[PRED]], label [[LOOP_LATCH]], label [[THEN:%.*]]
1157 ; TAILFOLD-NEXT: [[PRED:%.*]] = fcmp oeq float [[TMP0]], 0.000000e+00
1158 ; TAILFOLD-NEXT: br i1 [[PRED]], label [[LOOP_LATCH]], label [[THEN:%.*]]
/llvm-project-15.0.7/llvm/lib/BinaryFormat/
H A DDwarf.cpp544 #define HANDLE_DW_CFA_PRED(ID, NAME, PRED) \ in CallFrameString() argument
545 if (ID == Encoding && PRED) \ in CallFrameString()
552 #define HANDLE_DW_CFA_PRED(ID, NAME, PRED) in CallFrameString() argument
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/X86/
H A Dload-deref-pred.ll100 ; CHECK-NEXT: br i1 [[EARLYCND]], label [[PRED:%.*]], label [[LATCH]]
267 ; CHECK-NEXT: br i1 [[EARLYCND]], label [[PRED:%.*]], label [[LATCH]]
454 ; CHECK-NEXT: br i1 [[EARLYCND]], label [[PRED:%.*]], label [[LATCH]]
780 ; CHECK-NEXT: br i1 [[EARLYCND]], label [[PRED:%.*]], label [[LATCH]]
957 ; CHECK-NEXT: br i1 [[EARLYCND]], label [[PRED:%.*]], label [[LATCH]]
1130 ; CHECK-NEXT: br i1 [[EARLYCND]], label [[PRED:%.*]], label [[LATCH]]
1183 ; CHECK-NEXT: br i1 [[EARLYCND]], label [[PRED:%.*]], label [[LATCH]]
1481 ; CHECK-NEXT: br i1 [[EARLYCND]], label [[PRED:%.*]], label [[LATCH]]
1648 ; CHECK-NEXT: br i1 [[EARLYCND]], label [[PRED:%.*]], label [[LATCH]]
1815 ; CHECK-NEXT: br i1 [[EARLYCND]], label [[PRED:%.*]], label [[LATCH]]
[all …]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Hexagon/
H A Dxtype_pred.txt2 # Hexagon Programmer's Reference Manual 11.10.7 XTYPE/PRED
H A Dalu32_pred.txt2 # Hexagon Programmer's Reference Manual 11.1.3 ALU32/PRED
/llvm-project-15.0.7/llvm/lib/Transforms/Instrumentation/
H A DSanitizerCoverage.cpp526 return llvm::all_of(predecessors(BB), [&](const BasicBlock *PRED) { in isFullPostDominator() argument
527 return PDT->dominates(BB, PRED); in isFullPostDominator()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonIntrinsicsV5.td238 // ALU32/PRED
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/intrinsics/
H A Dxtype_pred.ll3 ; Hexagon Programmer's Reference Manual 11.10.7 XTYPE/PRED

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