Searched refs:PARITY (Results 1 – 9 of 9) sorted by relevance
| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 705 PARITY, enumerator
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 437 case ISD::PARITY: return "parity"; in getOperationName()
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| H A D | LegalizeIntegerTypes.cpp | 68 case ISD::PARITY: in PromoteIntegerResult()
2415 case ISD::PARITY: ExpandIntRes_PARITY(N, Lo, Hi); break; in ExpandIntegerResult()
3258 DAG.getNode(ISD::PARITY, dl, NVT, DAG.getNode(ISD::XOR, dl, NVT, Lo, Hi)); in ExpandIntRes_PARITY()
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| H A D | LegalizeDAG.cpp | 2724 case ISD::PARITY: in ExpandNode()
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| H A D | TargetLowering.cpp | 2153 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::PARITY, dl, VT, in SimplifyDemandedBits()
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| H A D | SelectionDAG.cpp | 3395 case ISD::PARITY: { in computeKnownBits()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 839 setOperationAction({ISD::BITREVERSE, ISD::PARITY}, VT, Expand); in initActions()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 535 setOperationAction(ISD::PARITY, MVT::i64, Custom); in AArch64TargetLowering()
536 setOperationAction(ISD::PARITY, MVT::i128, Custom); in AArch64TargetLowering()
5485 case ISD::PARITY: in LowerOperation()
7814 bool IsParity = Op.getOpcode() == ISD::PARITY; in LowerCTPOP_PARITY()
20258 case ISD::PARITY: in ReplaceNodeResults()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 425 setOperationAction(ISD::PARITY, MVT::i8, Custom); in X86TargetLowering()
426 setOperationAction(ISD::PARITY, MVT::i16, Custom); in X86TargetLowering()
427 setOperationAction(ISD::PARITY, MVT::i32, Custom); in X86TargetLowering()
429 setOperationAction(ISD::PARITY, MVT::i64, Custom); in X86TargetLowering()
32227 case ISD::PARITY: return LowerPARITY(Op, Subtarget, DAG); in LowerOperation()
43221 SDValue Result = DAG.getNode(ISD::PARITY, DL, CmpVT, Movmsk); in combinePredicateReduction()
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