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Searched refs:OutMI (Results 1 – 25 of 46) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsMCInstLower.cpp216 OutMI.setOpcode(Mips::LUi); in lowerLongBranchLUi()
219 OutMI.addOperand(LowerOperand(MI->getOperand(0))); in lowerLongBranchLUi()
244 OutMI.addOperand(MCOperand::createExpr(MipsExpr)); in lowerLongBranchLUi()
254 OutMI.setOpcode(Opcode); in lowerLongBranchADDiu()
278 OutMI.addOperand(LowerOperand(MO)); in lowerLongBranchADDiu()
302 lowerLongBranchLUi(MI, OutMI); in lowerLongBranch()
306 lowerLongBranchADDiu(MI, OutMI, Mips::ADDiu); in lowerLongBranch()
310 lowerLongBranchADDiu(MI, OutMI, Mips::DADDiu); in lowerLongBranch()
316 if (lowerLongBranch(MI, OutMI)) in Lower()
319 OutMI.setOpcode(MI->getOpcode()); in Lower()
[all …]
H A DMipsMCInstLower.h37 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
45 void lowerLongBranchLUi(const MachineInstr *MI, MCInst &OutMI) const;
46 void lowerLongBranchADDiu(const MachineInstr *MI, MCInst &OutMI,
48 bool lowerLongBranch(const MachineInstr *MI, MCInst &OutMI) const;
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVMCInstLower.cpp139 OutMI.setOpcode(RVV->BaseInstr); in lowerRISCVVMachineInstrToMCInst()
202 OutMI.addOperand(MCOp); in lowerRISCVVMachineInstrToMCInst()
215 if (lowerRISCVVMachineInstrToMCInst(MI, OutMI)) in lowerRISCVMachineInstrToMCInst()
218 OutMI.setOpcode(MI->getOpcode()); in lowerRISCVMachineInstrToMCInst()
223 OutMI.addOperand(MCOp); in lowerRISCVMachineInstrToMCInst()
226 switch (OutMI.getOpcode()) { in lowerRISCVMachineInstrToMCInst()
241 OutMI.setOpcode(RISCV::CSRRS); in lowerRISCVMachineInstrToMCInst()
242 OutMI.addOperand(MCOperand::createImm( in lowerRISCVMachineInstrToMCInst()
244 OutMI.addOperand(MCOperand::createReg(RISCV::X0)); in lowerRISCVMachineInstrToMCInst()
247 OutMI.setOpcode(RISCV::CSRRS); in lowerRISCVMachineInstrToMCInst()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyMCInstLower.cpp43 static void removeRegisterOperands(const MachineInstr *MI, MCInst &OutMI);
168 MCInst &OutMI) const { in lower()
169 OutMI.setOpcode(MI->getOpcode()); in lower()
264 OutMI.addOperand(MCOp); in lower()
268 removeRegisterOperands(MI, OutMI); in lower()
270 OutMI.insert(OutMI.begin(), MCOperand::createImm(MI->getNumExplicitDefs())); in lower()
291 auto RegOpcode = OutMI.getOpcode(); in removeRegisterOperands()
294 OutMI.setOpcode(StackOpcode); in removeRegisterOperands()
297 for (auto I = OutMI.getNumOperands(); I; --I) { in removeRegisterOperands()
298 auto &MO = OutMI.getOperand(I - 1); in removeRegisterOperands()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86MCInstLower.cpp535 OutMI.insert(OutMI.begin(), MCOperand::createReg(DestReg)); in Lower()
623 if (OutMI.getOperand(OutMI.getNumOperands() - 1).getImm() == 0) { in Lower()
690 OutMI.erase(&OutMI.getOperand(OutMI.getNumOperands() - 1)); in Lower()
695 if (OutMI.getOperand(OutMI.getNumOperands() - 1).getImm() == 6) { in Lower()
762 OutMI.erase(&OutMI.getOperand(OutMI.getNumOperands() - 1)); in Lower()
780 OutMI = MCInst(); in Lower()
810 OutMI.setOpcode(convertTailJumpOpcode(OutMI.getOpcode())); in Lower()
816 OutMI.setOpcode(convertTailJumpOpcode(OutMI.getOpcode())); in Lower()
824 OutMI.setOpcode(convertTailJumpOpcode(OutMI.getOpcode())); in Lower()
953 std::swap(OutMI.getOperand(1), OutMI.getOperand(2)); in Lower()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64MCInstLower.cpp302 void AArch64MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { in Lower()
303 OutMI.setOpcode(MI->getOpcode()); in Lower()
308 OutMI.addOperand(MCOp); in Lower()
311 switch (OutMI.getOpcode()) { in Lower()
313 OutMI = MCInst(); in Lower()
314 OutMI.setOpcode(AArch64::RET); in Lower()
315 OutMI.addOperand(MCOperand::createReg(AArch64::LR)); in Lower()
318 OutMI = MCInst(); in Lower()
319 OutMI.setOpcode(AArch64::RET); in Lower()
320 OutMI.addOperand(MCOperand::createReg(AArch64::LR)); in Lower()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600MCInstLower.cpp29 void lower(const MachineInstr *MI, MCInst &OutMI) const;
36 void R600MCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const { in lower()
37 OutMI.setOpcode(MI->getOpcode()); in lower()
41 OutMI.addOperand(MCOp); in lower()
H A DAMDGPUMCInstLower.cpp116 void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const { in lower()
128 OutMI.setOpcode(TII->pseudoToMCOpcode(AMDGPU::S_SWAPPC_B64)); in lower()
132 OutMI.addOperand(Dest); in lower()
133 OutMI.addOperand(Src); in lower()
147 OutMI.setOpcode(MCOpcode); in lower()
152 OutMI.addOperand(MCOp); in lower()
156 if (FIIdx >= (int)OutMI.getNumOperands()) in lower()
157 OutMI.addOperand(MCOperand::createImm(0)); in lower()
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kMCInstLower.cpp145 void M68kMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { in Lower()
147 OutMI.setOpcode(Opcode); in Lower()
154 OutMI.addOperand(MCOp.getValue()); in Lower()
159 assert(OutMI.getNumOperands() == 1 && "Unexpected number of operands"); in Lower()
168 OutMI.setOpcode(Opcode); in Lower()
/llvm-project-15.0.7/llvm/lib/Target/SPIRV/
H A DSPIRVMCInstLower.cpp23 void SPIRVMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI, in lower() argument
25 OutMI.setOpcode(MI->getOpcode()); in lower()
61 OutMI.addOperand(MCOp); in lower()
H A DSPIRVMCInstLower.h24 void lower(const MachineInstr *MI, MCInst &OutMI,
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFMCInstLower.cpp47 void BPFMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { in Lower()
48 OutMI.setOpcode(MI->getOpcode()); in Lower()
79 OutMI.addOperand(MCOp); in Lower()
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcMCInstLower.cpp94 MCInst &OutMI, in LowerSparcMachineInstrToMCInst() argument
98 OutMI.setOpcode(MI->getOpcode()); in LowerSparcMachineInstrToMCInst()
104 OutMI.addOperand(MCOp); in LowerSparcMachineInstrToMCInst()
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchMCInstLower.cpp82 MCInst &OutMI, AsmPrinter &AP) { in lowerLoongArchMachineInstrToMCInst() argument
83 OutMI.setOpcode(MI->getOpcode()); in lowerLoongArchMachineInstrToMCInst()
88 OutMI.addOperand(MCOp); in lowerLoongArchMachineInstrToMCInst()
H A DLoongArch.h29 bool lowerLoongArchMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEMCInstLower.cpp77 void llvm::LowerVEMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, in LowerVEMachineInstrToMCInst() argument
79 OutMI.setOpcode(MI->getOpcode()); in LowerVEMachineInstrToMCInst()
85 OutMI.addOperand(MCOp); in LowerVEMachineInstrToMCInst()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZMCInstLower.cpp94 void SystemZMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const { in lower()
95 OutMI.setOpcode(MI->getOpcode()); in lower()
99 OutMI.addOperand(lowerOperand(MO)); in lower()
/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCMCInstLower.cpp104 void ARCMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { in Lower()
105 OutMI.setOpcode(MI->getOpcode()); in Lower()
111 OutMI.addOperand(MCOp); in Lower()
/llvm-project-15.0.7/llvm/lib/Target/XCore/
H A DXCoreMCInstLower.cpp103 void XCoreMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { in Lower()
104 OutMI.setOpcode(MI->getOpcode()); in Lower()
110 OutMI.addOperand(MCOp); in Lower()
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYMCInstLower.cpp27 void CSKYMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { in Lower()
28 OutMI.setOpcode(MI->getOpcode()); in Lower()
33 OutMI.addOperand(MCOp); in Lower()
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRMCInstLower.cpp65 MCInst &OutMI) const { in lowerInstruction()
66 OutMI.setOpcode(MI.getOpcode()); in lowerInstruction()
109 OutMI.addOperand(MCOp); in lowerInstruction()
/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430MCInstLower.cpp115 void MSP430MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { in Lower()
116 OutMI.setOpcode(MI->getOpcode()); in Lower()
155 OutMI.addOperand(MCOp); in Lower()
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiMCInstLower.cpp93 void LanaiMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { in Lower()
94 OutMI.setOpcode(MI->getOpcode()); in Lower()
134 OutMI.addOperand(MCOp); in Lower()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMMCInstLower.cpp123 void llvm::LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, in LowerARMMachineInstrToMCInst() argument
125 OutMI.setOpcode(MI->getOpcode()); in LowerARMMachineInstrToMCInst()
163 OutMI.addOperand(MCOp); in LowerARMMachineInstrToMCInst()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCMCInstLower.cpp151 void llvm::LowerPPCMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, in LowerPPCMachineInstrToMCInst() argument
153 OutMI.setOpcode(MI->getOpcode()); in LowerPPCMachineInstrToMCInst()
158 OutMI.addOperand(MCOp); in LowerPPCMachineInstrToMCInst()

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