133                                             MCInst &OutMI) {  in lowerRISCVVMachineInstrToMCInst()  argument
139   OutMI.setOpcode(RVV->BaseInstr);  in lowerRISCVVMachineInstrToMCInst()
202     OutMI.addOperand(MCOp);  in lowerRISCVVMachineInstrToMCInst()
208     OutMI.addOperand(MCOperand::createReg(RISCV::NoRegister));  in lowerRISCVVMachineInstrToMCInst()
213 bool llvm::lowerRISCVMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,  in lowerRISCVMachineInstrToMCInst()  argument
215   if (lowerRISCVVMachineInstrToMCInst(MI, OutMI))  in lowerRISCVMachineInstrToMCInst()
218   OutMI.setOpcode(MI->getOpcode());  in lowerRISCVMachineInstrToMCInst()
223       OutMI.addOperand(MCOp);  in lowerRISCVMachineInstrToMCInst()
226   switch (OutMI.getOpcode()) {  in lowerRISCVMachineInstrToMCInst()
241     OutMI.setOpcode(RISCV::CSRRS);  in lowerRISCVMachineInstrToMCInst()
242     OutMI.addOperand(MCOperand::createImm(  in lowerRISCVMachineInstrToMCInst()
244     OutMI.addOperand(MCOperand::createReg(RISCV::X0));  in lowerRISCVMachineInstrToMCInst()
247     OutMI.setOpcode(RISCV::CSRRS);  in lowerRISCVMachineInstrToMCInst()
248     OutMI.addOperand(  in lowerRISCVMachineInstrToMCInst()
250     OutMI.addOperand(MCOperand::createReg(RISCV::X0));  in lowerRISCVMachineInstrToMCInst()