| /llvm-project-15.0.7/llvm/tools/llvm-readobj/ |
| H A D | ARMEHABIPrinter.h | 112 uint8_t Opcode1 = Opcodes[OI++ ^ 3]; in Decode_1000iiii_iiiiiiii() local
159 uint8_t Opcode1 = Opcodes[OI++ ^ 3]; in Decode_10110001_0000iiii() local
163 if (((Opcode1 & 0xf0) == 0x00) && Opcode1) in Decode_10110001_0000iiii()
164 PrintGPR((Opcode1 & 0x0f)); in Decode_10110001_0000iiii()
187 uint8_t Opcode1 = Opcodes[OI++ ^ 3]; in Decode_10110011_sssscccc() local
210 uint8_t Opcode1 = Opcodes[OI++ ^ 3]; in Decode_11000110_sssscccc() local
220 uint8_t Opcode1 = Opcodes[OI++ ^ 3]; in Decode_11000111_0000iiii() local
223 ((Opcode1 & 0xf0) || Opcode1 == 0x00) ? "spare" : "pop "); in Decode_11000111_0000iiii()
224 if ((Opcode1 & 0xf0) == 0x00 && Opcode1) in Decode_11000111_0000iiii()
231 uint8_t Opcode1 = Opcodes[OI++ ^ 3]; in Decode_11001000_sssscccc() local
[all …]
|
| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86TargetTransformInfo.h | 244 bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
|
| H A D | X86TargetTransformInfo.cpp | 5359 unsigned Opcode1, in isLegalAltInstr() argument
5375 unsigned Opc = OpcodeMask.test(Lane) ? Opcode1 : Opcode0; in isLegalAltInstr()
|
| H A D | X86ISelLowering.cpp | 40308 unsigned Opcode1 = N1.getOpcode(); in combineTargetShuffle() local
40309 if (Opcode1 == ISD::FADD || Opcode1 == ISD::FMUL || Opcode1 == ISD::FSUB || in combineTargetShuffle()
40310 Opcode1 == ISD::FDIV) { in combineTargetShuffle()
40314 (N11 == N0 && (Opcode1 == ISD::FADD || Opcode1 == ISD::FMUL))) { in combineTargetShuffle()
40321 SDValue Scl = DAG.getNode(Opcode1, DL, SVT, N10, N11); in combineTargetShuffle()
|
| /llvm-project-15.0.7/llvm/include/llvm/Analysis/ |
| H A D | TargetTransformInfo.h | 696 bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
1612 unsigned Opcode1,
2041 bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, in isLegalAltInstr() argument
2043 return Impl.isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask); in isLegalAltInstr()
|
| H A D | TargetTransformInfoImpl.h | 282 bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, in isLegalAltInstr() argument
|
| /llvm-project-15.0.7/llvm/lib/Analysis/ |
| H A D | TargetTransformInfo.cpp | 418 VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, in isLegalAltInstr() argument
420 return TTIImpl->isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask); in isLegalAltInstr()
|
| /llvm-project-15.0.7/llvm/lib/Transforms/Scalar/ |
| H A D | Reassociate.cpp | 164 static BinaryOperator *isReassociableOp(Value *V, unsigned Opcode1, in isReassociableOp() argument
168 (BO->getOpcode() == Opcode1 || BO->getOpcode() == Opcode2)) in isReassociableOp()
|
| /llvm-project-15.0.7/llvm/lib/Transforms/Vectorize/ |
| H A D | SLPVectorizer.cpp | 3745 unsigned Opcode1 = TE->getAltOpcode(); in reorderTopToBottom() local
3749 if (cast<Instruction>(TE->Scalars[Lane])->getOpcode() == Opcode1) in reorderTopToBottom()
3752 if (TTIRef.isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask)) { in reorderTopToBottom()
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 3270 int64_t Offset1, unsigned Opcode1, int FI2, in shouldClusterFI() argument
3279 int Scale1 = AArch64InstrInfo::getMemScale(Opcode1); in shouldClusterFI()
|
| H A D | AArch64ISelLowering.cpp | 13812 unsigned Opcode1 = SUB->getOperand(1).getOpcode(); in performVecReduceAddCombineWithUADDLP() local
13820 if (Opcode0 == ISD::ZERO_EXTEND && Opcode1 == ISD::ZERO_EXTEND) { in performVecReduceAddCombineWithUADDLP()
13822 } else if (Opcode0 == ISD::SIGN_EXTEND && Opcode1 == ISD::SIGN_EXTEND) { in performVecReduceAddCombineWithUADDLP()
|
| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 5098 unsigned Opcode1 = isSignedMinMax(N00, N01, N02, N03, N0CC); in isSaturatingMinMax() local
5099 if (!Opcode1 || Opcode0 == Opcode1) in isSaturatingMinMax()
|