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Searched refs:Opc0 (Results 1 – 5 of 5) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/
H A DInstCombineVectorOps.cpp2090 BinaryOperator::BinaryOps Opc0 = B0->getOpcode(); in foldSelectShuffle() local
2093 if (ConstantsAreOp1 && Opc0 != Opc1) { in foldSelectShuffle()
2097 if (Opc0 == Instruction::Shl || Opc1 == Instruction::Shl) in foldSelectShuffle()
2101 Opc0 = AltB0.Opcode; in foldSelectShuffle()
2110 if (Opc0 != Opc1 || !C0 || !C1) in foldSelectShuffle()
2114 BinaryOperator::BinaryOps BOpc = Opc0; in foldSelectShuffle()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp87 unsigned Opc0 = N0->getMachineOpcode(); in nodesHaveSameOperandValue() local
90 int Op0Idx = AMDGPU::getNamedOperandIdx(Opc0, OpName); in nodesHaveSameOperandValue()
181 unsigned Opc0 = Load0->getMachineOpcode(); in areLoadsFromSameBasePtr() local
185 if (!get(Opc0).mayLoad() || !get(Opc1).mayLoad()) in areLoadsFromSameBasePtr()
188 if (isDS(Opc0) && isDS(Opc1)) { in areLoadsFromSameBasePtr()
210 Offset0Idx -= get(Opc0).NumDefs; in areLoadsFromSameBasePtr()
217 if (isSMRD(Opc0) && isSMRD(Opc1)) { in areLoadsFromSameBasePtr()
219 if (AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::sbase) == -1 || in areLoadsFromSameBasePtr()
250 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1))) { in areLoadsFromSameBasePtr()
258 int OffIdx0 = AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::offset); in areLoadsFromSameBasePtr()
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/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp26538 Opc = IntrData->Opc0; in LowerINTRINSIC_WO_CHAIN()
26572 Opc = IntrData->Opc0; in LowerINTRINSIC_WO_CHAIN()
26654 Opc = IntrData->Opc0; in LowerINTRINSIC_WO_CHAIN()
26693 unsigned Opc = IntrData->Opc0; in LowerINTRINSIC_WO_CHAIN()
26732 Opc = IntrData->Opc0; in LowerINTRINSIC_WO_CHAIN()
26766 unsigned Opc = IntrData->Opc0; in LowerINTRINSIC_WO_CHAIN()
26787 Opc = IntrData->Opc0; in LowerINTRINSIC_WO_CHAIN()
26803 unsigned Opc = IntrData->Opc0; in LowerINTRINSIC_WO_CHAIN()
27028 unsigned Opc = IntrData->Opc0; in LowerINTRINSIC_WO_CHAIN()
47942 unsigned Opc0 = N0.getOpcode(); in combineAnd() local
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H A DX86IntrinsicsInfo.h47 uint16_t Opc0; member
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp6650 unsigned Opc0 = N0.getOpcode(); in isBSwapHWordElement() local
6651 if (Opc0 != ISD::AND && Opc0 != ISD::SHL && Opc0 != ISD::SRL) in isBSwapHWordElement()
6658 else if (Opc0 == ISD::AND) in isBSwapHWordElement()
6672 if (Opc == ISD::SRL || (Opc == ISD::AND && Opc0 == ISD::SHL)) { in isBSwapHWordElement()
6686 if (Opc0 != ISD::SRL) in isBSwapHWordElement()
6694 if (Opc0 != ISD::SHL) in isBSwapHWordElement()
9857 unsigned Opc0 = Op0.getOpcode(); in combineABSToABD() local
9859 if (Opc0 != Op1.getOpcode() || in combineABSToABD()
9860 (Opc0 != ISD::ZERO_EXTEND && Opc0 != ISD::SIGN_EXTEND)) in combineABSToABD()
9866 unsigned ABDOpcode = (Opc0 == ISD::SIGN_EXTEND) ? ISD::ABDS : ISD::ABDU; in combineABSToABD()