| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsSEInstrInfo.cpp | 50 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) { in isLoadFromStackSlot()
72 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) { in isStoreToStackSlot()
660 return (Opc == Mips::BEQ || Opc == Mips::BEQ_MM || Opc == Mips::BNE || in getAnalyzableBrOpc()
661 Opc == Mips::BNE_MM || Opc == Mips::BGTZ || Opc == Mips::BGEZ || in getAnalyzableBrOpc()
662 Opc == Mips::BLTZ || Opc == Mips::BLEZ || Opc == Mips::BEQ64 || in getAnalyzableBrOpc()
663 Opc == Mips::BNE64 || Opc == Mips::BGTZ64 || Opc == Mips::BGEZ64 || in getAnalyzableBrOpc()
664 Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 || Opc == Mips::BC1T || in getAnalyzableBrOpc()
665 Opc == Mips::BC1F || Opc == Mips::B || Opc == Mips::J || in getAnalyzableBrOpc()
675 Opc == Mips::BLTZC64 || Opc == Mips::BLEZC64 || Opc == Mips::BC || in getAnalyzableBrOpc()
676 Opc == Mips::BBIT0 || Opc == Mips::BBIT1 || Opc == Mips::BBIT032 || in getAnalyzableBrOpc()
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| H A D | Mips16InstrInfo.cpp | 73 unsigned Opc = 0; in copyPhysReg() local
115 unsigned Opc = 0; in storeRegToStack() local
133 unsigned Opc = 0; in loadRegFromStack() local
159 switch (Opc) { in getOppositeBranchOpc()
435 return (Opc == Mips::BeqzRxImmX16 || Opc == Mips::BimmX16 || in getAnalyzableBrOpc()
437 Opc == Mips::Bteqz16 || Opc == Mips::Btnez16 || in getAnalyzableBrOpc()
438 Opc == Mips::BeqzRxImm16 || Opc == Mips::BnezRxImm16 || in getAnalyzableBrOpc()
439 Opc == Mips::BnezRxImmX16 || Opc == Mips::BteqzX16 || in getAnalyzableBrOpc()
443 Opc == Mips::BtnezX16 || Opc == Mips::BtnezT8CmpX16 || in getAnalyzableBrOpc()
444 Opc == Mips::BtnezT8CmpiX16 || Opc == Mips::BtnezT8SltX16 || in getAnalyzableBrOpc()
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| /llvm-project-15.0.7/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelDAGToDAG.cpp | 747 unsigned Opc; in SelectAddrSpaceCast() local
776 unsigned Opc; in SelectAddrSpaceCast() local
2341 unsigned Opc = 0; in tryTextureIntrinsic() local
2346 Opc = NVPTX::TEX_1D_F32_S32_RR; in tryTextureIntrinsic()
2349 Opc = NVPTX::TEX_1D_F32_F32_RR; in tryTextureIntrinsic()
2860 unsigned Opc = 0; in trySurfaceIntrinsic() local
3547 unsigned Opc; in tryBFE() local
3552 Opc = NVPTX::BFE_S32rii; in tryBFE()
3554 Opc = NVPTX::BFE_U32rii; in tryBFE()
3558 Opc = NVPTX::BFE_S64rii; in tryBFE()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.h | 564 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B; in isUncondBranchOpcode()
640 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc; in isCondBranchOpcode()
644 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm_i12 || in isJumpTableBranchOpcode()
645 Opc == ARM::BR_JTm_rs || Opc == ARM::BR_JTadd || Opc == ARM::tBR_JTr || in isJumpTableBranchOpcode()
651 return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND; in isIndirectBranchOpcode()
717 Opc == ARM::t2LDMIA_RET || Opc == ARM::tPOP || Opc == ARM::LDMIA_UPD || in isPopOpcode()
722 return Opc == ARM::tPUSH || Opc == ARM::t2STMDB_UPD || in isPushOpcode()
728 Opc == ARM::tSUBi3 || Opc == ARM::tSUBi8 || in isSubImmOpcode()
729 Opc == ARM::tSUBSi3 || Opc == ARM::tSUBSi8 || in isSubImmOpcode()
730 Opc == ARM::t2SUBri || Opc == ARM::t2SUBri12 || Opc == ARM::t2SUBSri; in isSubImmOpcode()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CSEMIRBuilder.cpp | 63 if (!CSEInfo || !CSEInfo->shouldCSE(Opc)) in canPerformCSEForOpc()
105 B.addNodeIDOpcode(Opc); in profileMBBOpcode()
113 profileMBBOpcode(B, Opc); in profileEverything()
174 switch (Opc) { in buildInstr()
200 if (Opc == TargetOpcode::G_PTR_ADD && in buildInstr()
277 if (!canPerformCSEForOpc(Opc)) in buildInstr()
305 constexpr unsigned Opc = TargetOpcode::G_CONSTANT; in buildConstant() local
306 if (!canPerformCSEForOpc(Opc)) in buildConstant()
317 profileMBBOpcode(ProfBuilder, Opc); in buildConstant()
333 if (!canPerformCSEForOpc(Opc)) in buildFConstant()
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| H A D | CSEInfo.cpp | 37 bool CSEConfigFull::shouldCSEOpc(unsigned Opc) { in shouldCSEOpc() argument
38 switch (Opc) { in shouldCSEOpc()
70 return Opc == TargetOpcode::G_CONSTANT || Opc == TargetOpcode::G_FCONSTANT || in shouldCSEOpc()
71 Opc == TargetOpcode::G_IMPLICIT_DEF; in shouldCSEOpc()
168 void GISelCSEInfo::countOpcodeHit(unsigned Opc) { in countOpcodeHit() argument
170 if (OpcodeHitTable.count(Opc)) in countOpcodeHit()
171 OpcodeHitTable[Opc] += 1; in countOpcodeHit()
173 OpcodeHitTable[Opc] = 1; in countOpcodeHit()
222 bool GISelCSEInfo::shouldCSE(unsigned Opc) const { in shouldCSE()
224 return CSEOpt->shouldCSEOpc(Opc); in shouldCSE()
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| /llvm-project-15.0.7/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyFastISel.cpp | 605 unsigned Opc = in fastMaterializeAlloca() local
662 unsigned Opc; in fastLowerArguments() local
929 unsigned Opc; in selectSelect() local
936 Opc = WebAssembly::SELECT_I32; in selectSelect()
940 Opc = WebAssembly::SELECT_I64; in selectSelect()
944 Opc = WebAssembly::SELECT_F32; in selectSelect()
1030 unsigned Opc; in selectICmp() local
1099 unsigned Opc; in selectFCmp() local
1198 unsigned Opc; in selectLoad() local
1257 unsigned Opc; in selectStore() local
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| /llvm-project-15.0.7/llvm/lib/Target/WebAssembly/MCTargetDesc/ |
| H A D | WebAssemblyMCTargetDesc.h | 139 switch (Opc) { in GetDefaultP2AlignAny()
276 switch (Opc) { in isArgument()
307 inline bool isCopy(unsigned Opc) { in isCopy() argument
308 switch (Opc) { in isCopy()
329 inline bool isTee(unsigned Opc) { in isTee() argument
330 switch (Opc) { in isTee()
352 switch (Opc) { in isCallDirect()
364 switch (Opc) { in isCallIndirect()
388 switch (Opc) { in isMarker()
407 inline bool isCatch(unsigned Opc) { in isCatch() argument
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| /llvm-project-15.0.7/llvm/utils/TableGen/ |
| H A D | WebAssemblyDisassemblerEmitter.cpp | 41 unsigned Opc = static_cast<unsigned>( in emitWebAssemblyDisassemblerTables() local
44 if (Opc == 0xFFFFFFFF) in emitWebAssemblyDisassemblerTables()
46 assert(Opc <= 0xFFFFFF); in emitWebAssemblyDisassemblerTables()
48 if (Opc <= 0xFFFF) { in emitWebAssemblyDisassemblerTables()
49 Prefix = Opc >> 8; in emitWebAssemblyDisassemblerTables()
50 Opc = Opc & 0xFF; in emitWebAssemblyDisassemblerTables()
52 Prefix = Opc >> 16; in emitWebAssemblyDisassemblerTables()
53 Opc = Opc & 0xFFFF; in emitWebAssemblyDisassemblerTables()
55 auto &CGIP = OpcodeTable[Prefix][Opc]; in emitWebAssemblyDisassemblerTables()
|
| /llvm-project-15.0.7/llvm/lib/Target/RISCV/MCTargetDesc/ |
| H A D | RISCVMatInt.cpp | 23 switch (Instr.Opc) { in getInstSeqCost()
268 unsigned Opc; in generateInstSeq() local
270 Opc = RISCV::BCLRI; in generateInstSeq()
273 Opc = RISCV::BSETI; in generateInstSeq()
289 Opc = 0; in generateInstSeq()
294 Opc = RISCV::BSETI; in generateInstSeq()
296 Opc = RISCV::BCLRI; in generateInstSeq()
300 if (Opc > 0) { in generateInstSeq()
316 unsigned Opc = 0; in generateInstSeq() local
321 Opc = RISCV::SH1ADD; in generateInstSeq()
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| /llvm-project-15.0.7/llvm/include/llvm/IR/ |
| H A D | ConstantFolder.h | 48 if (ConstantExpr::isDesirableBinOp(Opc)) in FoldBinOp()
49 return ConstantExpr::get(Opc, LC, RC); in FoldBinOp()
50 return ConstantFoldBinaryInstruction(Opc, LC, RC); in FoldBinOp()
60 if (ConstantExpr::isDesirableBinOp(Opc)) in FoldExactBinOp()
61 return ConstantExpr::get(Opc, LC, RC, in FoldExactBinOp()
63 return ConstantFoldBinaryInstruction(Opc, LC, RC); in FoldExactBinOp()
73 if (ConstantExpr::isDesirableBinOp(Opc)) { in FoldNoWrapBinOp()
79 return ConstantExpr::get(Opc, LC, RC, Flags); in FoldNoWrapBinOp()
81 return ConstantFoldBinaryInstruction(Opc, LC, RC); in FoldNoWrapBinOp()
88 return FoldBinOp(Opc, LHS, RHS); in FoldBinOpFMF()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 182 switch (Opc) { in getBranchDisplacementBits()
598 return Opc; in canFoldIntoCSel()
999 switch (Opc) { in isSEHInstruction()
2147 switch (Opc) { in hasUnscaledLdStOffset()
2182 switch (Opc) { in getUnscaledLdSt()
2212 switch (Opc) { in getLoadStoreImmIdx()
2387 switch (Opc) { in convertToFlagSettingOpc()
3054 switch (Opc) { in getMemScale()
4243 switch (Opc) { in emitFrameOffsetAdj()
4738 switch (Opc) { in isCombineInstrSettingFlag()
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| H A D | AArch64InstrInfo.h | 82 static bool hasUnscaledLdStOffset(unsigned Opc);
92 static int getMemScale(unsigned Opc);
122 static unsigned getLoadStoreImmIdx(unsigned Opc);
308 bool isPTestLikeOpcode(unsigned Opc) const;
310 bool isWhileOpcode(unsigned Opc) const;
459 static inline bool isUncondBranchOpcode(int Opc) { return Opc == AArch64::B; } in isUncondBranchOpcode() argument
461 static inline bool isCondBranchOpcode(int Opc) { in isCondBranchOpcode() argument
462 switch (Opc) { in isCondBranchOpcode()
479 switch (Opc) { in isIndirectBranchOpcode()
490 static inline bool isPTrueOpcode(unsigned Opc) { in isPTrueOpcode() argument
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| /llvm-project-15.0.7/llvm/include/llvm/Analysis/ |
| H A D | TargetFolder.h | 54 Value *FoldBinOp(Instruction::BinaryOps Opc, Value *LHS, in FoldBinOp() argument
59 if (ConstantExpr::isDesirableBinOp(Opc)) in FoldBinOp()
60 return Fold(ConstantExpr::get(Opc, LC, RC)); in FoldBinOp()
61 return ConstantFoldBinaryOpOperands(Opc, LC, RC, DL); in FoldBinOp()
71 if (ConstantExpr::isDesirableBinOp(Opc)) in FoldExactBinOp()
74 return ConstantFoldBinaryOpOperands(Opc, LC, RC, DL); in FoldExactBinOp()
84 if (ConstantExpr::isDesirableBinOp(Opc)) { in FoldNoWrapBinOp()
90 return Fold(ConstantExpr::get(Opc, LC, RC, Flags)); in FoldNoWrapBinOp()
99 return FoldBinOp(Opc, LHS, RHS); in FoldBinOpFMF()
110 Value *FoldUnOpFMF(Instruction::UnaryOps Opc, Value *V, in FoldUnOpFMF() argument
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| H A D | InstSimplifyFolder.h | 50 Value *FoldBinOp(Instruction::BinaryOps Opc, Value *LHS, in FoldBinOp() argument
52 return simplifyBinOp(Opc, LHS, RHS, SQ); in FoldBinOp()
55 Value *FoldExactBinOp(Instruction::BinaryOps Opc, Value *LHS, Value *RHS, in FoldExactBinOp() argument
57 return simplifyBinOp(Opc, LHS, RHS, SQ); in FoldExactBinOp()
60 Value *FoldNoWrapBinOp(Instruction::BinaryOps Opc, Value *LHS, Value *RHS, in FoldNoWrapBinOp() argument
62 return simplifyBinOp(Opc, LHS, RHS, SQ); in FoldNoWrapBinOp()
65 Value *FoldBinOpFMF(Instruction::BinaryOps Opc, Value *LHS, Value *RHS, in FoldBinOpFMF() argument
67 return simplifyBinOp(Opc, LHS, RHS, FMF, SQ); in FoldBinOpFMF()
70 Value *FoldUnOpFMF(Instruction::UnaryOps Opc, Value *V, in FoldUnOpFMF() argument
72 return simplifyUnOp(Opc, V, FMF, SQ); in FoldUnOpFMF()
|
| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 453 unsigned Opc; in PPCEmitLoad() local
491 Opc = PPC::LD; in PPCEmitLoad()
553 switch (Opc) { in PPCEmitLoad()
622 unsigned Opc; in PPCEmitStore() local
703 switch (Opc) { in PPCEmitStore()
1089 unsigned Opc; in SelectIToFP() local
1133 unsigned Opc; in SelectIToFP() local
1225 unsigned Opc; in SelectFPToI() local
1286 unsigned Opc; in SelectBinaryIntOp() local
1817 unsigned Opc; in PPCEmitIntExt() local
[all …]
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| H A D | PPCCTRLoopsVerify.cpp | 117 unsigned Opc = I->getOpcode(); in verifyCTRBranch() local
118 if (Opc == PPC::MTCTRloop || Opc == PPC::MTCTR8loop) { in verifyCTRBranch()
175 unsigned Opc = MII->getOpcode(); in runOnMachineFunction() local
176 if (Opc == PPC::BDNZ8 || Opc == PPC::BDNZ || in runOnMachineFunction()
177 Opc == PPC::BDZ8 || Opc == PPC::BDZ) in runOnMachineFunction()
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| /llvm-project-15.0.7/llvm/lib/Target/ARC/ |
| H A D | ARCFrameLowering.cpp | 137 unsigned Opc = ARC::SUB_rrlimm; in emitPrologue() local
139 Opc = ARC::SUB_rru6; in emitPrologue()
141 Opc = ARC::SUB_rrs12; in emitPrologue()
256 Opc = ARC::SUB_rru6; in emitEpilogue()
284 Opc = ARC::ADD_rru6; in emitEpilogue()
286 Opc = ARC::ADD_rrs12; in emitEpilogue()
299 Opc = ARC::ADD_rru6; in emitEpilogue()
301 Opc = ARC::ADD_rrs12; in emitEpilogue()
326 Opc = ARC::ADD_rru6; in emitEpilogue()
328 Opc = ARC::ADD_rrs12; in emitEpilogue()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86FastISel.cpp | 335 unsigned Opc = 0; in X86FastEmitLoad() local
492 unsigned Opc = 0; in X86FastEmitStore() local
680 if (Opc) { in X86FastEmitStore()
2278 unsigned Opc; in X86FastEmitPseudoSelect() local
2494 unsigned Opc = in X86SelectFPExt() local
2508 unsigned Opc = in X86SelectFPTrunc() local
2671 unsigned Opc; in fastLowerIntrinsicCall() local
2813 unsigned Opc; in fastLowerIntrinsicCall() local
3002 unsigned Opc; in fastLowerIntrinsicCall() local
3857 if (Opc) { in fastMaterializeConstant()
[all …]
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | XRayInstrumentation.cpp | 96 unsigned Opc = 0; in replaceRetWithPatchableRet() local
101 Opc = TargetOpcode::PATCHABLE_RET; in replaceRetWithPatchableRet()
106 Opc = TargetOpcode::PATCHABLE_TAIL_CALL; in replaceRetWithPatchableRet()
108 if (Opc != 0) { in replaceRetWithPatchableRet()
109 auto MIB = BuildMI(MBB, T, T.getDebugLoc(), TII->get(Opc)) in replaceRetWithPatchableRet()
129 unsigned Opc = 0; in prependRetWithPatchableExit() local
132 Opc = TargetOpcode::PATCHABLE_FUNCTION_EXIT; in prependRetWithPatchableExit()
135 Opc = TargetOpcode::PATCHABLE_TAIL_CALL; in prependRetWithPatchableExit()
137 if (Opc != 0) { in prependRetWithPatchableExit()
140 BuildMI(MBB, T, T.getDebugLoc(), TII->get(Opc)); in prependRetWithPatchableExit()
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| /llvm-project-15.0.7/clang/lib/StaticAnalyzer/Checkers/ |
| H A D | ConversionChecker.cpp | 81 BinaryOperator::Opcode Opc = B->getOpcode(); in checkPreStmt() local
82 if (Opc == BO_Assign) { in checkPreStmt()
87 } else if (Opc == BO_AddAssign || Opc == BO_SubAssign) { in checkPreStmt()
90 } else if (Opc == BO_MulAssign) { in checkPreStmt()
93 } else if (Opc == BO_DivAssign || Opc == BO_RemAssign) { in checkPreStmt()
96 } else if (Opc == BO_AndAssign) { in checkPreStmt()
99 } else if (Opc == BO_OrAssign || Opc == BO_XorAssign) { in checkPreStmt()
|
| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/Utils/ |
| H A D | AMDGPUBaseInfo.h | 419 int getMTBUFElements(unsigned Opc);
422 bool getMTBUFHasVAddr(unsigned Opc);
425 bool getMTBUFHasSrsrc(unsigned Opc);
437 int getMUBUFElements(unsigned Opc);
440 bool getMUBUFHasVAddr(unsigned Opc);
452 bool getSMEMIsBuffer(unsigned Opc);
455 bool getVOP1IsSingle(unsigned Opc);
458 bool getVOP2IsSingle(unsigned Opc);
461 bool getVOP3IsSingle(unsigned Opc);
464 bool isVOPC64DPP(unsigned Opc);
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonGenPredicate.cpp | 120 bool isScalarCmp(unsigned Opc);
147 switch (Opc) { in getPredForm()
189 unsigned Opc = MI->getOpcode(); in isConvertibleToPredForm() local
190 if (getPredForm(Opc) != 0) in isConvertibleToPredForm()
197 switch (Opc) { in isConvertibleToPredForm()
211 switch (Opc) { in collectPredicateGPR()
256 unsigned Opc = DefI->getOpcode(); in getPredRegFor() local
257 if (Opc == Hexagon::C2_tfrpr || Opc == TargetOpcode::COPY) { in getPredRegFor()
286 switch (Opc) { in isScalarCmp()
370 unsigned Opc = MI->getOpcode(); in convertToPredForm() local
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIPreAllocateWWMRegs.cpp | 164 unsigned Opc = MI.getOpcode(); in printWWMInfo() local
166 if (Opc == AMDGPU::ENTER_STRICT_WWM || Opc == AMDGPU::ENTER_STRICT_WQM) { in printWWMInfo()
169 assert(Opc == AMDGPU::EXIT_STRICT_WWM || Opc == AMDGPU::EXIT_STRICT_WQM); in printWWMInfo()
173 if (Opc == AMDGPU::ENTER_STRICT_WWM || Opc == AMDGPU::EXIT_STRICT_WWM) { in printWWMInfo()
176 assert(Opc == AMDGPU::ENTER_STRICT_WQM || Opc == AMDGPU::EXIT_STRICT_WQM); in printWWMInfo()
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| /llvm-project-15.0.7/llvm/lib/Target/LoongArch/MCTargetDesc/ |
| H A D | LoongArchMatInt.h | 18 unsigned Opc; member
20 Inst(unsigned Opc, int64_t Imm) : Opc(Opc), Imm(Imm) {} in Inst()
|