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Searched refs:OpSize (Results 1 – 25 of 37) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsRegisterBankInfo.h75 bool isAmbiguous_64(InstType InstTy, unsigned OpSize) const { in isAmbiguous_64() argument
76 if (InstTy == InstType::Ambiguous && OpSize == 64) in isAmbiguous_64()
81 bool isAmbiguous_32(InstType InstTy, unsigned OpSize) const { in isAmbiguous_32() argument
82 if (InstTy == InstType::Ambiguous && OpSize == 32) in isAmbiguous_32()
87 bool isAmbiguous_32or64(InstType InstTy, unsigned OpSize) const { in isAmbiguous_32or64() argument
88 if (InstTy == InstType::Ambiguous && (OpSize == 32 || OpSize == 64)) in isAmbiguous_32or64()
94 unsigned OpSize) const { in isAmbiguousWithMergeOrUnmerge_64() argument
101 if (InstTy == InstType::FloatingPoint && (OpSize == 32 || OpSize == 64)) in isFloatingPoint_32or64()
107 if (InstTy == InstType::FloatingPoint && OpSize == 64) in isFloatingPoint_64()
112 bool isInteger_32(InstType InstTy, unsigned OpSize) const { in isInteger_32() argument
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/llvm-project-15.0.7/llvm/utils/TableGen/
H A DX86RecognizableInstr.h175 uint8_t OpSize; member
258 bool hasREX_W, uint8_t OpSize);
269 uint8_t OpSize);
274 uint8_t OpSize);
279 uint8_t OpSize);
281 uint8_t OpSize);
283 uint8_t OpSize);
285 uint8_t OpSize);
287 uint8_t OpSize);
289 uint8_t OpSize);
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H A DX86RecognizableInstr.cpp117 OpSize = byteFromRec(Rec, "OpSizeBits"); in RecognizableInstrBase()
349 if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) in insnContext()
397 uint8_t OpSize)) { in handleOperand() argument
419 typeFromString(std::string(typeName), HasREX_W, OpSize); in handleOperand()
885 uint8_t OpSize) { in typeFromString() argument
891 if(OpSize == X86Local::OpSize16) { in typeFromString()
895 } else if(OpSize == X86Local::OpSize32) { in typeFromString()
1027 uint8_t OpSize) { in immediateEncodingFromString() argument
1028 if(OpSize != X86Local::OpSize16) { in immediateEncodingFromString()
1193 uint8_t OpSize) { in memoryEncodingFromString() argument
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H A DX86FoldTablesEmitter.cpp295 RegRI.OpSize != MemRI.OpSize || RegRI.AdSize != MemRI.AdSize || in operator ()()
/llvm-project-15.0.7/llvm/lib/MC/MCDisassembler/
H A DMCExternalSymbolizer.cpp36 bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) { in tryAddingSymbolicOperand() argument
42 !GetOpInfo(DisInfo, Address, Offset, OpSize, InstSize, 1, &SymbolicOp)) { in tryAddingSymbolicOperand()
55 if (!SymbolLookUp || (OpSize == 1 && !IsBranch)) in tryAddingSymbolicOperand()
H A DMCDisassembler.cpp30 uint64_t Offset, uint64_t OpSize, in tryAddingSymbolicOperand() argument
35 OpSize, InstSize); in tryAddingSymbolicOperand()
/llvm-project-15.0.7/llvm/unittests/MC/X86/
H A DX86MCDisassemblerTest.cpp81 uint64_t Offset, uint64_t OpSize, in tryAddingSymbolicOperand() argument
83 Operands.push_back({Value, Offset, OpSize}); in tryAddingSymbolicOperand()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMLegalizerInfo.cpp404 auto OpSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits(); in legalizeCustom() local
409 auto Libcalls = getFCmpLibcalls(Predicate, OpSize); in legalizeCustom()
421 assert((OpSize == 32 || OpSize == 64) && "Unsupported operand size"); in legalizeCustom()
422 auto *ArgTy = OpSize == 32 ? Type::getFloatTy(Ctx) : Type::getDoubleTy(Ctx); in legalizeCustom()
H A DARMInstructionSelector.cpp460 unsigned OpRegBank, unsigned OpSize) in CmpConstants()
463 OperandSize(OpSize) {} in CmpConstants()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64ExternalSymbolizer.h32 uint64_t Offset, uint64_t OpSize,
H A DAArch64ExternalSymbolizer.cpp63 bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) { in tryAddingSymbolicOperand() argument
76 if (!GetOpInfo || !GetOpInfo(DisInfo, Address, /*Offset=*/0, OpSize, InstSize, in tryAddingSymbolicOperand()
/llvm-project-15.0.7/bolt/lib/Target/X86/
H A DX86MCSymbolizer.h33 uint64_t Offset, uint64_t OpSize,
/llvm-project-15.0.7/llvm/include/llvm/MC/MCDisassembler/
H A DMCExternalSymbolizer.h49 uint64_t Offset, uint64_t OpSize,
H A DMCSymbolizer.h72 uint64_t OpSize, uint64_t InstSize) = 0;
H A DMCDisassembler.h208 bool IsBranch, uint64_t Offset, uint64_t OpSize,
/llvm-project-15.0.7/llvm/include/llvm-c/
H A DDisassemblerTypes.h49 uint64_t OpSize, uint64_t InstSize,
/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64RegisterBankInfo.cpp676 SmallVector<unsigned, 4> OpSize(NumOperands); in getInstrMapping() local
684 OpSize[Idx] = Ty.getSizeInBits(); in getInstrMapping()
752 OpSize[0]); in getInstrMapping()
992 auto Mapping = getValueMapping(OpRegBankIdx[Idx], OpSize[Idx]); in getInstrMapping()
H A DAArch64InstructionSelector.cpp751 unsigned OpSize) { in selectBinaryOp() argument
754 if (OpSize == 32) { in selectBinaryOp()
765 } else if (OpSize == 64) { in selectBinaryOp()
781 switch (OpSize) { in selectBinaryOp()
822 unsigned OpSize) { in selectLoadStoreUIOp() argument
826 switch (OpSize) { in selectLoadStoreUIOp()
838 switch (OpSize) { in selectLoadStoreUIOp()
3006 const unsigned OpSize = Ty.getSizeInBits(); in select() local
4612 unsigned OpSize = Ty.getSizeInBits(); in emitFPCompare() local
4613 if (OpSize != 32 && OpSize != 64) in emitFPCompare()
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/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.h280 uint64_t Offset, uint64_t OpSize,
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DGISelKnownBits.cpp488 unsigned OpSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits(); in computeKnownBitsImpl() local
494 Known.insertBits(SrcOpKnown, I * OpSize); in computeKnownBitsImpl()
/llvm-project-15.0.7/llvm/lib/ObjectYAML/
H A DDWARFEmitter.cpp836 if (Expected<uint64_t> OpSize = in writeListEntry() local
838 DescriptionsLength += *OpSize; in writeListEntry()
840 return OpSize.takeError(); in writeListEntry()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetInstrInfo.cpp582 int64_t OpSize = MFI.getObjectSize(FI); in foldMemoryOperand() local
587 OpSize = SubRegSize / 8; in foldMemoryOperand()
590 MemSize = std::max(MemSize, OpSize); in foldMemoryOperand()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrFormats.td194 class OpSize16 { OperandSize OpSize = OpSize16; }
195 class OpSize32 { OperandSize OpSize = OpSize32; }
308 OperandSize OpSize = OpSizeFixed; // Does this instruction's encoding change
310 bits<2> OpSizeBits = OpSize.Value;
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Drotate4.ll6 ; a << (b & (OpSize-1)) | a >> ((0 - b) & (OpSize-1))
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPURegisterBankInfo.cpp879 unsigned OpSize = OpTy.getSizeInBits(); in executeInWaterfallLoop() local
880 bool Is64 = OpSize % 64 == 0; in executeInWaterfallLoop()
883 unsigned NumParts = OpSize / PartSize; in executeInWaterfallLoop()
4345 unsigned OpSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits(); in getInstrMapping() local
4346 OpdsMapping[2] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, OpSize); in getInstrMapping()
4347 OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, OpSize); in getInstrMapping()

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