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Searched refs:OpReg (Results 1 – 16 of 16) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/MCA/
H A DAMDGPUCustomBehaviour.cpp188 const MCAOperand *OpReg = Inst.getOperand(0); in computeWaitCnt() local
190 assert(OpReg && OpReg->isReg() && "First operand should be a register."); in computeWaitCnt()
192 if (OpReg->getReg() != AMDGPU::SGPR_NULL) { in computeWaitCnt()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86FastISel.cpp1741 .addReg(OpReg).addImm(1); in X86SelectBranch()
1773 if (OpReg == 0) return false; in X86SelectBranch()
1777 unsigned KOpReg = OpReg; in X86SelectBranch()
1782 OpReg = fastEmitInst_extractsubreg(MVT::i8, OpReg, X86::sub_8bit); in X86SelectBranch()
1785 .addReg(OpReg) in X86SelectBranch()
1794 unsigned CReg = 0, OpReg = 0; in X86SelectShift() local
2366 if (OpReg == 0) in X86SelectSelect()
2372 .addReg(OpReg); in X86SelectSelect()
2411 if (OpReg == 0) in X86SelectIntToFP()
2465 if (OpReg == 0) in X86SelectFPExtOrFPTrunc()
[all …]
H A DX86SpeculativeLoadHardening.cpp1660 Register OpReg = Op->getReg(); in hardenLoadAddr() local
1661 auto *OpRC = MRI->getRegClass(OpReg); in hardenLoadAddr()
1699 .addReg(OpReg); in hardenLoadAddr()
1730 .addReg(OpReg); in hardenLoadAddr()
1743 .addReg(OpReg); in hardenLoadAddr()
1752 .addReg(OpReg) in hardenLoadAddr()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DA15SDOptimizer.cpp297 Register OpReg = MI->getOperand(I).getReg(); in optimizeSDPattern() local
299 if (!Register::isVirtualRegister(OpReg)) in optimizeSDPattern()
302 MachineInstr *Def = MRI->getVRegDef(OpReg); in optimizeSDPattern()
H A DARMInstructionSelector.cpp1043 Register OpReg = I.getOperand(2).getReg(); in select() local
1044 unsigned Size = MRI.getType(OpReg).getSizeInBits(); in select()
H A DARMFastISel.cpp1263 Register OpReg = getRegForValue(TI->getOperand(0)); in SelectBranch() local
1264 OpReg = constrainOperandRegClass(TII.get(TstOpc), OpReg, 0); in SelectBranch()
1267 .addReg(OpReg).addImm(1)); in SelectBranch()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPURegisterBankInfo.cpp864 Register OpReg = Op.getReg(); in executeInWaterfallLoop() local
865 LLT OpTy = MRI.getType(OpReg); in executeInWaterfallLoop()
867 const RegisterBank *OpBank = getRegBank(OpReg, MRI, *TRI); in executeInWaterfallLoop()
871 OpReg = B.buildCopy(OpTy, OpReg).getReg(0); in executeInWaterfallLoop()
872 MRI.setRegBank(OpReg, AMDGPU::VGPRRegBank); in executeInWaterfallLoop()
876 Register CurrentLaneReg = buildReadFirstLane(B, MRI, OpReg); in executeInWaterfallLoop()
888 OpParts.push_back(OpReg); in executeInWaterfallLoop()
891 auto UnmergeOp = B.buildUnmerge(PartTy, OpReg); in executeInWaterfallLoop()
3421 Register OpReg = MI.getOperand(I).getReg(); in getImageMapping() local
3423 if (!OpReg) in getImageMapping()
[all …]
H A DAMDGPUInstructionSelector.cpp2293 Register OpReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectG_FNEG() local
2304 BuildMI(*BB, &MI, DL, TII.get(Opc), OpReg) in selectG_FNEG()
2310 .addReg(OpReg) in selectG_FNEG()
2330 Register OpReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectG_FABS() local
2345 BuildMI(*BB, &MI, DL, TII.get(AMDGPU::S_AND_B32), OpReg) in selectG_FABS()
2351 .addReg(OpReg) in selectG_FABS()
H A DSIInstrInfo.cpp5434 Register OpReg = Op.getReg(); in legalizeGenericOperand() local
5438 RI.getRegClassForReg(MRI, OpReg), OpSubReg); in legalizeGenericOperand()
5450 MachineInstr *Def = MRI.getVRegDef(OpReg); in legalizeGenericOperand()
5456 FoldImmediate(*Copy, *Def, OpReg, &MRI); in legalizeGenericOperand()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp1601 Register OpReg = getRegForValue(In); in selectFNeg() local
1602 if (!OpReg) in selectFNeg()
1608 OpReg); in selectFNeg()
1623 ISD::BITCAST, OpReg); in selectFNeg()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DMachineInstr.cpp1895 Register OpReg = MO.getReg(); in clearRegisterKills() local
1896 if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg) in clearRegisterKills()
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp5201 Register OpReg = MI.getOperand(0).getReg(); in narrowScalarExtract() local
5203 uint64_t OpSize = MRI.getType(OpReg).getSizeInBits(); in narrowScalarExtract()
5267 Register OpReg = MI.getOperand(2).getReg(); in narrowScalarInsert() local
5269 uint64_t OpSize = MRI.getType(OpReg).getSizeInBits(); in narrowScalarInsert()
5273 if (DstStart == OpStart && NarrowTy == MRI.getType(OpReg)) { in narrowScalarInsert()
5276 DstRegs.push_back(OpReg); in narrowScalarInsert()
5308 Register SegReg = OpReg; in narrowScalarInsert()
5312 MIRBuilder.buildExtract(SegReg, OpReg, ExtractOffset); in narrowScalarInsert()
7287 Register OpReg = MI.getOperand(1).getReg(); in lowerAbsToAddXor() local
7290 auto Shift = MIRBuilder.buildAShr(DstTy, OpReg, ShiftAmt); in lowerAbsToAddXor()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp4541 unsigned OpReg = Inst.getOperand(2).getReg(); in expandSge() local
4558 TOut.emitRRR(OpCode, DstReg, SrcReg, OpReg, IDLoc, STI); in expandSge()
4678 unsigned OpReg = Inst.getOperand(2).getReg(); in expandSle() local
4695 TOut.emitRRR(OpCode, DstReg, OpReg, SrcReg, IDLoc, STI); in expandSle()
5369 unsigned OpReg = Inst.getOperand(2).getReg(); in expandSeq() local
5373 if (SrcReg != Mips::ZERO && OpReg != Mips::ZERO) { in expandSeq()
5374 TOut.emitRRR(Mips::XOR, DstReg, SrcReg, OpReg, IDLoc, STI); in expandSeq()
5379 unsigned Reg = SrcReg == Mips::ZERO ? OpReg : SrcReg; in expandSeq()
5450 unsigned OpReg = Inst.getOperand(2).getReg(); in expandSne() local
5454 if (SrcReg != Mips::ZERO && OpReg != Mips::ZERO) { in expandSne()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/
H A DX86InstComments.cpp251 unsigned OpReg = MI->getOperand(OperandIndex).getReg(); in getRegOperandNumElts() local
252 return getVectorRegSize(OpReg) / ScalarSize; in getRegOperandNumElts()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp6812 Register OpReg = MO.getReg(); in fixupPHIOpBanks() local
6813 const RegisterBank *RB = MRI.getRegBankOrNull(OpReg); in fixupPHIOpBanks()
6816 auto *OpDef = MRI.getVRegDef(OpReg); in fixupPHIOpBanks()
6817 const LLT &Ty = MRI.getType(OpReg); in fixupPHIOpBanks()
6826 auto Copy = MIB.buildCopy(Ty, OpReg); in fixupPHIOpBanks()
/llvm-project-15.0.7/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp7499 unsigned OpReg = Inst.getOperand(i).getReg(); in checkLowRegisterList() local
7500 if (OpReg == Reg) in checkLowRegisterList()
7503 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg)) in checkLowRegisterList()
7513 unsigned OpReg = Inst.getOperand(i).getReg(); in listContainsReg() local
7514 if (OpReg == Reg) in listContainsReg()