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Searched refs:Op3 (Results 1 – 25 of 34) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/XCore/Disassembler/
H A DXCoreDisassembler.cpp514 unsigned Op1, Op2, Op3; in Decode3RInstruction() local
527 unsigned Op1, Op2, Op3; in Decode3RImmInstruction() local
540 unsigned Op1, Op2, Op3; in Decode2RUSInstruction() local
553 unsigned Op1, Op2, Op3; in Decode2RUSBitpInstruction() local
566 unsigned Op1, Op2, Op3; in DecodeL3RInstruction() local
580 unsigned Op1, Op2, Op3; in DecodeL3RSrcDstInstruction() local
595 unsigned Op1, Op2, Op3; in DecodeL2RUSInstruction() local
609 unsigned Op1, Op2, Op3; in DecodeL2RUSBitpInstruction() local
657 unsigned Op1, Op2, Op3, Op4, Op5; in DecodeL5RInstruction() local
677 unsigned Op1, Op2, Op3; in DecodeL4RSrcDstInstruction() local
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/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblySelectionDAGInfo.h27 SDValue Op3, Align Alignment, bool isVolatile,
33 SDValue Op1, SDValue Op2, SDValue Op3,
39 SDValue Op3, Align Alignment, bool IsVolatile,
H A DWebAssemblySelectionDAGInfo.cpp38 SDValue Op3, Align Alignment, bool IsVolatile, in EmitTargetCodeForMemmove() argument
40 return EmitTargetCodeForMemcpy(DAG, DL, Chain, Op1, Op2, Op3, in EmitTargetCodeForMemmove()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DSelectionDAGTargetInfo.h53 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcpy() argument
69 SDValue Op2, SDValue Op3, Align Alignment, bool isVolatile, in EmitTargetCodeForMemmove() argument
83 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemset() argument
96 SDValue Op1, SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcmp() argument
H A DSelectionDAG.h1550 SDValue Op3);
1552 SDValue Op3, SDValue Op4);
1554 SDValue Op3, SDValue Op4, SDValue Op5);
1582 SDValue Op1, SDValue Op2, SDValue Op3);
1617 SDValue Op1, SDValue Op2, SDValue Op3);
1623 EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
1630 SDValue Op3);
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrBuilder.h110 const MachineOperand &Op3 = MI->getOperand(Operand + 3); in getAddressFromInstr() local
111 if (Op3.isGlobal()) in getAddressFromInstr()
112 AM.GV = Op3.getGlobal(); in getAddressFromInstr()
114 AM.Disp = Op3.getImm(); in getAddressFromInstr()
H A DX86FastISel.cpp169 unsigned Op1, unsigned Op2, unsigned Op3);
3979 unsigned Op2, unsigned Op3) { in fastEmitInst_rrrr() argument
3986 Op3 = constrainOperandRegClass(II, Op3, II.getNumDefs() + 3); in fastEmitInst_rrrr()
3993 .addReg(Op3); in fastEmitInst_rrrr()
3999 .addReg(Op3); in fastEmitInst_rrrr()
/llvm-project-15.0.7/llvm/lib/Target/XCore/
H A DXCoreSelectionDAGInfo.h24 SDValue Op3, Align Alignment, bool isVolatile,
/llvm-project-15.0.7/llvm/lib/Target/BPF/AsmParser/
H A DBPFAsmParser.cpp272 BPFOperand &Op3 = (BPFOperand &)*Operands[3]; in PreMatchCheck() local
273 if (Op0.isReg() && Op1.isToken() && Op2.isToken() && Op3.isReg() in PreMatchCheck()
279 && Op0.getReg() != Op3.getReg()) in PreMatchCheck()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMSelectionDAGInfo.h57 SDValue Op3, Align Alignment, bool isVolatile,
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPURegBankCombiner.cpp295 MachineInstr *Op3 = getDefIgnoringCopies(MI.getOperand(4).getReg(), MRI); in matchFPMed3ToClamp() local
296 if (Op3->getOpcode() == TargetOpcode::G_FCONSTANT) in matchFPMed3ToClamp()
297 return Op3->getOperand(1).getFPImm()->isExactlyValue(0.0); in matchFPMed3ToClamp()
H A DR600InstrFormats.td28 bit Op3 = 0;
54 let TSFlags{5} = Op3;
/llvm-project-15.0.7/llvm/include/llvm/IR/
H A DPatternMatch.h1444 T2 Op3; member
1446 ThreeOps_match(const T0 &Op1, const T1 &Op2, const T2 &Op3) in ThreeOps_match()
1447 : Op1(Op1), Op2(Op2), Op3(Op3) {} in ThreeOps_match()
1453 Op3.match(I->getOperand(2)); in match()
2105 const Opnd3 &Op3) {
2106 return m_Intrinsic<Intrinsic::masked_load>(Op0, Op1, Op2, Op3);
2113 const Opnd3 &Op3) {
2114 return m_Intrinsic<Intrinsic::masked_gather>(Op0, Op1, Op2, Op3);
2144 m_Intrinsic(const T0 &Op0, const T1 &Op1, const T2 &Op2, const T3 &Op3,
2146 return m_CombineAnd(m_Intrinsic<IntrID>(Op0, Op1, Op2, Op3),
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/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DSVEInstrFormats.td359 (inst $Op3, $Op1, $Op2)>;
367 (inst $Op3, $Op1, $Op2)>;
375 (inst $Op3, $Op1, $Op2)>;
382 (inst $Op3, $Op1, $Op2)>;
415 (inst $Op1, $Op2, $Op3)>;
420 (inst $Op1, $Op2, $Op3)>;
427 (inst $Op1, $Op2, $Op3)>;
460 (inst $Op1, $Op2, $Op3)>;
466 (inst $Op1, $Op2, vt3:$Op3)>;
528 (inst $Op2, $Op3, $Op1)>;
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64InstPrinter.cpp86 const MCOperand &Op3 = MI->getOperand(3); in printInst() local
90 if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) { in printInst()
93 switch (Op3.getImm()) { in printInst()
126 if (Op2.isImm() && Op3.isImm()) { in printInst()
130 int64_t imms = Op3.getImm(); in printInst()
160 if (Op2.getImm() > Op3.getImm()) { in printInst()
163 << ", #" << (Is64Bit ? 64 : 32) - Op2.getImm() << ", #" << Op3.getImm() + 1; in printInst()
171 << ", #" << Op2.getImm() << ", #" << Op3.getImm() - Op2.getImm() + 1; in printInst()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp5489 AArch64Operand &Op3 = static_cast<AArch64Operand &>(*Operands[3]); in MatchAndEmitInstruction() local
5490 if (Op2.isScalarReg() && Op3.isImm()) { in MatchAndEmitInstruction()
5511 NewOp4, Op3.getStartLoc(), Op3.getEndLoc(), getContext())); in MatchAndEmitInstruction()
5578 if (Op1.isScalarReg() && Op3.isImm() && Op4.isImm()) { in MatchAndEmitInstruction()
5594 return Error(Op3.getStartLoc(), in MatchAndEmitInstruction()
5617 NewOp3, Op3.getStartLoc(), Op3.getEndLoc(), getContext()); in MatchAndEmitInstruction()
5642 if (Op1.isScalarReg() && Op3.isImm() && Op4.isImm()) { in MatchAndEmitInstruction()
5658 return Error(Op3.getStartLoc(), in MatchAndEmitInstruction()
5699 if ((Op1.isToken() && Op2.isNeonVectorReg() && Op3.isImm()) || in MatchAndEmitInstruction()
5700 (Op1.isNeonVectorReg() && Op2.isToken() && Op3.isImm())) { in MatchAndEmitInstruction()
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/llvm-project-15.0.7/llvm/unittests/Transforms/Vectorize/
H A DVPlanTest.cpp831 VPValue Op3; in TEST() local
835 Args.push_back(&Op3); in TEST()
981 VPValue Op3; in TEST() local
985 Args.push_back(&Op3); in TEST()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp1336 const MachineOperand &Op3 = MI.getOperand(3); in expandPostRAPseudo() local
1340 Register Rt = Op3.getReg(); in expandPostRAPseudo()
1344 unsigned K3 = getKillRegState(Op3.isKill()); in expandPostRAPseudo()
1360 const MachineOperand &Op3 = MI.getOperand(3); in expandPostRAPseudo() local
1368 unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill in expandPostRAPseudo()
1378 if (Op0.getReg() != Op3.getReg()) { in expandPostRAPseudo()
1382 .add(Op3); in expandPostRAPseudo()
1393 MachineOperand &Op3 = MI.getOperand(3); in expandPostRAPseudo() local
1414 if (Op0.getReg() != Op3.getReg()) { in expandPostRAPseudo()
1415 Register SrcLo = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_lo); in expandPostRAPseudo()
[all …]
H A DHexagonSplitDouble.cpp904 MachineOperand &Op3 = MI->getOperand(3); in splitAslOr() local
905 assert(Op0.isReg() && Op1.isReg() && Op2.isReg() && Op3.isImm()); in splitAslOr()
906 int64_t Sh64 = Op3.getImm(); in splitAslOr()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsTargetStreamer.h137 MCOperand Op3, SMLoc IDLoc, const MCSubtargetInfo *STI);
/llvm-project-15.0.7/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsTargetStreamer.cpp233 unsigned Reg2, MCOperand Op3, SMLoc IDLoc, in emitRRRX() argument
240 TmpInst.addOperand(Op3); in emitRRRX()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp9360 SDValue Ops[] = { Op1, Op2, Op3 }; in UpdateNodeOperands()
9366 SDValue Op3, SDValue Op4) { in UpdateNodeOperands() argument
9367 SDValue Ops[] = { Op1, Op2, Op3, Op4 }; in UpdateNodeOperands()
9373 SDValue Op3, SDValue Op4, SDValue Op5) { in UpdateNodeOperands() argument
9374 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 }; in UpdateNodeOperands()
9469 SDValue Ops[] = { Op1, Op2, Op3 }; in SelectNodeTo()
9674 SDValue Op3) { in getMachineNode() argument
9676 SDValue Ops[] = { Op1, Op2, Op3 }; in getMachineNode()
9698 SDValue Ops[] = { Op1, Op2, Op3 }; in getMachineNode()
9720 SDValue Op3) { in getMachineNode() argument
[all …]
H A DSelectionDAGBuilder.cpp5863 SDValue Op3 = getValue(I.getArgOperand(2)); in visitIntrinsicCall() local
5874 Root, sdl, Op1, Op2, Op3, Alignment, isVol, in visitIntrinsicCall()
5905 SDValue Op3 = getValue(I.getArgOperand(2)); in visitIntrinsicCall() local
5912 Root, sdl, Op1, Op2, Op3, Alignment, isVol, /* AlwaysInline */ false, in visitIntrinsicCall()
5939 SDValue Op3 = getValue(I.getArgOperand(2)); in visitIntrinsicCall() local
5949 SDValue MM = DAG.getMemmove(Root, sdl, Op1, Op2, Op3, Alignment, isVol, in visitIntrinsicCall()
6563 SDValue Op3 = getValue(I.getArgOperand(2)); in visitIntrinsicCall() local
6565 Op1.getValueType(), Op1, Op2, Op3)); in visitIntrinsicCall()
6574 SDValue Op3 = getValue(I.getArgOperand(2)); in visitIntrinsicCall() local
6576 Op1, Op2, Op3, DAG, TLI)); in visitIntrinsicCall()
/llvm-project-15.0.7/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp6660 const auto &Op3 = static_cast<ARMOperand &>(*Operands[3]); in tryConvertingToTwoOperandForm() local
6662 if (!Op3.isReg() || !Op4.isReg()) in tryConvertingToTwoOperandForm()
6665 auto Op3Reg = Op3.getReg(); in tryConvertingToTwoOperandForm()
6983 ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]); in fixupGNULDRDAlias() local
6987 if (!Op3.isGPRMem()) in fixupGNULDRDAlias()
7065 const MCParsedAsmOperand &Op3 = *Operands[3 + NumPredOps]; in CDEConvertDualRegOperand() local
7066 if (!Op3.isReg() || Op3.getReg() != RNext) in CDEConvertDualRegOperand()
7067 return Error(Op3.getStartLoc(), "operand must be a consecutive register"); in CDEConvertDualRegOperand()
/llvm-project-15.0.7/llvm/lib/IR/
H A DVerifier.cpp5422 auto *Op3 = cast<ConstantInt>(Call.getArgOperand(2)); in visitIntrinsicCall() local
5423 Check(Op3->getType()->getBitWidth() <= 32, in visitIntrinsicCall()
5428 Check(Op3->getZExtValue() < Op1->getType()->getScalarSizeInBits(), in visitIntrinsicCall()
5432 Check(Op3->getZExtValue() <= Op1->getType()->getScalarSizeInBits(), in visitIntrinsicCall()

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