1336       const MachineOperand &Op3 = MI.getOperand(3);  in expandPostRAPseudo()  local
1340       Register Rt = Op3.getReg();  in expandPostRAPseudo()
1344       unsigned K3 = getKillRegState(Op3.isKill());  in expandPostRAPseudo()
1360       const MachineOperand &Op3 = MI.getOperand(3);  in expandPostRAPseudo()  local
1368         unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill  in expandPostRAPseudo()
1378       if (Op0.getReg() != Op3.getReg()) {  in expandPostRAPseudo()
1382                      .add(Op3);  in expandPostRAPseudo()
1393       MachineOperand &Op3 = MI.getOperand(3);  in expandPostRAPseudo()  local
1401         unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill  in expandPostRAPseudo()
1414       if (Op0.getReg() != Op3.getReg()) {  in expandPostRAPseudo()
1415         Register SrcLo = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_lo);  in expandPostRAPseudo()
1416         Register SrcHi = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_hi);  in expandPostRAPseudo()