Home
last modified time | relevance | path

Searched refs:Op2 (Results 1 – 25 of 125) sorted by relevance

12345

/llvm-project-15.0.7/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiMCCodeEmitter.cpp145 ((Op2.isImm() && Op2.getImm() != 0) || in adjustPqBits()
146 (Op2.isReg() && Op2.getReg() != Lanai::R0) || (Op2.isExpr()))) in adjustPqBits()
153 if (LPAC::modifiesOp(AluCode) && ((Op2.isImm() && Op2.getImm() != 0) || in adjustPqBits()
154 (Op2.isReg() && Op2.getReg() != Lanai::R0))) in adjustPqBits()
194 assert((Op2.isImm() || Op2.isExpr()) && in getRiMemoryOpValue()
200 if (Op2.isImm()) { in getRiMemoryOpValue()
201 assert(isInt<16>(Op2.getImm()) && in getRiMemoryOpValue()
205 if (Op2.getImm() != 0) { in getRiMemoryOpValue()
265 assert((Op2.isImm() || Op2.isExpr()) && in getSplsOpValue()
271 if (Op2.isImm()) { in getSplsOpValue()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/XCore/Disassembler/
H A DXCoreDisassembler.cpp322 unsigned Op1, Op2; in Decode2RInstruction() local
335 unsigned Op1, Op2; in Decode2RImmInstruction() local
348 unsigned Op1, Op2; in DecodeR2RInstruction() local
361 unsigned Op1, Op2; in Decode2RSrcDstInstruction() local
375 unsigned Op1, Op2; in DecodeRUSInstruction() local
388 unsigned Op1, Op2; in DecodeRUSBitpInstruction() local
401 unsigned Op1, Op2; in DecodeRUSSrcDstBitpInstruction() local
486 unsigned Op1, Op2; in DecodeL2RInstruction() local
500 unsigned Op1, Op2; in DecodeLR2RInstruction() local
514 unsigned Op1, Op2, Op3; in Decode3RInstruction() local
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiMemAluCombiner.cpp170 bool isSameOperand(const MachineOperand &Op1, const MachineOperand &Op2) { in isSameOperand() argument
171 if (Op1.getType() != Op2.getType()) in isSameOperand()
176 return Op1.getReg() == Op2.getReg(); in isSameOperand()
178 return Op1.getImm() == Op2.getImm(); in isSameOperand()
294 MachineOperand &Op2 = AluIter->getOperand(2); in isSuitableAluInstr() local
301 if (Op2.isImm()) { in isSuitableAluInstr()
314 ((IsSpls && isInt<10>(Op2.getImm())) || in isSuitableAluInstr()
315 (!IsSpls && isInt<16>(Op2.getImm())))) || in isSuitableAluInstr()
316 Offset.getImm() == Op2.getImm())) in isSuitableAluInstr()
318 } else if (Op2.isReg()) { in isSuitableAluInstr()
[all …]
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DDFAPacketizer.cpp283 const MachineMemOperand &Op2, in alias() argument
285 if (!Op1.getValue() || !Op2.getValue()) in alias()
288 int64_t MinOffset = std::min(Op1.getOffset(), Op2.getOffset()); in alias()
290 int64_t Overlapb = Op2.getSize() + Op2.getOffset() - MinOffset; in alias()
295 MemoryLocation(Op2.getValue(), Overlapb, in alias()
296 UseTBAA ? Op2.getAAInfo() : AAMDNodes())); in alias()
308 for (const MachineMemOperand *Op2 : MI2.memoperands()) in alias() local
309 if (alias(*Op1, *Op2, UseTBAA)) in alias()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/Utils/
H A DAArch64BaseInfo.cpp142 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; in parseGenericRegister() local
148 Ops[5].getAsInteger(10, Op2); in parseGenericRegister()
149 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2; in parseGenericRegister()
160 uint32_t Op2 = Bits & 0x7; in genericRegisterString() local
163 utostr(CRm) + "_" + utostr(Op2); in genericRegisterString()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIPreEmitPeephole.cpp117 MachineOperand &Op2 = A->getOperand(2); in optimizeVccBranch() local
118 if (Op1.getReg() != ExecReg && Op2.isReg() && Op2.getReg() == ExecReg) { in optimizeVccBranch()
124 if (Op2.isImm() && !(Op2.getImm() == -1 || Op2.getImm() == 0)) in optimizeVccBranch()
129 if (Op2.isReg()) { in optimizeVccBranch()
130 SReg = Op2.getReg(); in optimizeVccBranch()
159 if (!ReadsSreg && Op2.isKill()) { in optimizeVccBranch()
163 } else if (Op2.isImm()) { in optimizeVccBranch()
164 MaskValue = Op2.getImm(); in optimizeVccBranch()
H A DSIOptimizeExecMaskingPreRA.cpp155 MachineOperand *Op2 = TII->getNamedOperand(*Cmp, AMDGPU::OpName::src1); in optimizeVcndVcmpPair() local
156 if (Op1->isImm() && Op2->isReg()) in optimizeVcndVcmpPair()
157 std::swap(Op1, Op2); in optimizeVcndVcmpPair()
158 if (!Op1->isReg() || !Op2->isImm() || Op2->getImm() != 1) in optimizeVcndVcmpPair()
174 Op2 = TII->getNamedOperand(*Sel, AMDGPU::OpName::src1); in optimizeVcndVcmpPair()
176 if (!Op1->isImm() || !Op2->isImm() || !CC->isReg() || in optimizeVcndVcmpPair()
177 Op1->getImm() != 0 || Op2->getImm() != 1) in optimizeVcndVcmpPair()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DSelectionDAGTargetInfo.h53 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcpy() argument
69 SDValue Op2, SDValue Op3, Align Alignment, bool isVolatile, in EmitTargetCodeForMemmove() argument
83 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemset() argument
96 SDValue Op1, SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcmp() argument
133 SDValue Op1, SDValue Op2, in EmitTargetCodeForStrcmp() argument
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblySelectionDAGInfo.h26 SDValue Chain, SDValue Op1, SDValue Op2,
33 SDValue Op1, SDValue Op2, SDValue Op3,
38 SDValue Chain, SDValue Op1, SDValue Op2,
H A DWebAssemblyPeephole.cpp141 const auto &Op2 = MI.getOperand(2); in runOnMachineFunction() local
142 if (!Op2.isReg()) in runOnMachineFunction()
147 Register NewReg = Op2.getReg(); in runOnMachineFunction()
H A DWebAssemblySelectionDAGInfo.cpp37 SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Op1, SDValue Op2, in EmitTargetCodeForMemmove() argument
40 return EmitTargetCodeForMemcpy(DAG, DL, Chain, Op1, Op2, Op3, in EmitTargetCodeForMemmove()
/llvm-project-15.0.7/llvm/lib/Target/BPF/AsmParser/
H A DBPFAsmParser.cpp271 BPFOperand &Op2 = (BPFOperand &)*Operands[2]; in PreMatchCheck() local
273 if (Op0.isReg() && Op1.isToken() && Op2.isToken() && Op3.isReg() in PreMatchCheck()
275 && (Op2.getToken() == "-" || Op2.getToken() == "be16" in PreMatchCheck()
276 || Op2.getToken() == "be32" || Op2.getToken() == "be64" in PreMatchCheck()
277 || Op2.getToken() == "le16" || Op2.getToken() == "le32" in PreMatchCheck()
278 || Op2.getToken() == "le64") in PreMatchCheck()
/llvm-project-15.0.7/llvm/lib/Target/Sparc/MCTargetDesc/
H A DSparcInstPrinter.cpp153 const MCOperand &Op2 = MI->getOperand(opNum + 1); in printMemOperand() local
164 PrintedFirstOperand && ((Op2.isReg() && Op2.getReg() == SP::G0) || in printMemOperand()
165 (Op2.isImm() && Op2.getImm() == 0)); in printMemOperand()
/llvm-project-15.0.7/llvm/unittests/Transforms/Vectorize/
H A DVPlanTest.cpp771 VPValue Op2; in TEST() local
786 VPValue Op2; in TEST() local
805 VPValue Op2; in TEST() local
830 VPValue Op2; in TEST() local
858 VPValue Op2; in TEST() local
881 VPValue Op2; in TEST() local
909 VPValue Op2; in TEST() local
964 VPValue Op2; in TEST() local
980 VPValue Op2; in TEST() local
999 VPValue Op2; in TEST() local
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonSplitDouble.cpp347 int32_t Prof2 = Op2.isImm() ? profitImm(Op2.getImm()) : 0; in profit()
727 MachineOperand &Op2 = MI->getOperand(2); in splitCombine() local
744 if (!Op2.isReg()) { in splitCombine()
746 .add(Op2); in splitCombine()
749 .addReg(Op2.getReg(), getRegState(Op2), Op2.getSubReg()); in splitCombine()
781 int64_t Sh64 = Op2.getImm(); in splitShift()
919 unsigned RS2 = getRegState(Op2); in splitAslOr()
946 .addReg(Op2.getReg(), RS2, HiSR); in splitAslOr()
963 .addReg(Op2.getReg(), RS2, HiSR) in splitAslOr()
974 .addReg(Op2.getReg(), RS2, LoSR); in splitAslOr()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYISelDAGToDAG.cpp298 auto Op2 = N->getOperand(2); in selectAddCarry() local
302 if (isNullConstant(Op2)) { in selectAddCarry()
308 } else if (isOneConstant(Op2)) { in selectAddCarry()
317 Dl, {Type0, Type1}, {Op0, Op1, Op2}); in selectAddCarry()
341 auto Op2 = N->getOperand(2); in selectSubCarry() local
345 if (isNullConstant(Op2)) { in selectSubCarry()
351 } else if (isOneConstant(Op2)) { in selectSubCarry()
358 auto CarryIn = InvertCarryFlag(Subtarget, CurDAG, Dl, Op2); in selectSubCarry()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCBranchCoalescing.cpp342 const MachineOperand &Op2 = OpList2[i]; in identicalOperands() local
345 << "Op2: " << Op2 << "\n"); in identicalOperands()
347 if (Op1.isIdenticalTo(Op2)) { in identicalOperands()
364 if (Op1.isReg() && Op2.isReg() && in identicalOperands()
366 Register::isVirtualRegister(Op2.getReg())) { in identicalOperands()
368 MachineInstr *Op2Def = MRI->getVRegDef(Op2.getReg()); in identicalOperands()
H A DPPCMacroFusion.cpp72 const MachineOperand &Op2 = SecondMI.getOperand(SecondMIOpIndex); in matchingRegOps() local
73 if (!Op1.isReg() || !Op2.isReg()) in matchingRegOps()
76 return Op1.getReg() == Op2.getReg(); in matchingRegOps()
/llvm-project-15.0.7/llvm/lib/Transforms/Utils/
H A DBypassSlowDivision.cpp89 Value *insertOperandRuntimeCheck(Value *Op1, Value *Op2);
330 Value *FastDivInsertionTask::insertOperandRuntimeCheck(Value *Op1, Value *Op2) { in insertOperandRuntimeCheck() argument
331 assert((Op1 || Op2) && "Nothing to check"); in insertOperandRuntimeCheck()
336 if (Op1 && Op2) in insertOperandRuntimeCheck()
337 OrV = Builder.CreateOr(Op1, Op2); in insertOperandRuntimeCheck()
339 OrV = Op1 ? Op1 : Op2; in insertOperandRuntimeCheck()
/llvm-project-15.0.7/llvm/lib/Target/BPF/MCTargetDesc/
H A DBPFMCCodeEmitter.cpp161 MCOperand Op2 = MI.getOperand(MemOpStartIndex + 1); in getMemoryOpValue() local
162 assert(Op2.isImm() && "Second operand is not immediate."); in getMemoryOpValue()
163 Encoding |= Op2.getImm() & 0xffff; in getMemoryOpValue()
/llvm-project-15.0.7/llvm/unittests/ADT/
H A DAPFloatTest.cpp4146 Op2[0], Op2[1]) in TEST()
4210 Op2[0], Op2[1]) in TEST()
4214 Op2[0], Op2[1]) in TEST()
4314 Op2[0], Op2[1]) in TEST()
4387 Op2[0], Op2[1]) in TEST()
4391 Op2[0], Op2[1]) in TEST()
4467 Op2[0], Op2[1]) in TEST()
4471 Op1[1], Op2[0], Op2[1]) in TEST()
4502 Op2[0], Op2[1]) in TEST()
4506 Op2[0], Op2[1]) in TEST()
[all …]
/llvm-project-15.0.7/llvm/include/llvm/IR/
H A DPatternMatch.h1426 T1 Op2; member
1428 TwoOps_match(const T0 &Op1, const T1 &Op2) : Op1(Op1), Op2(Op2) {} in TwoOps_match()
1443 T1 Op2; member
1446 ThreeOps_match(const T0 &Op1, const T1 &Op2, const T2 &Op3) in ThreeOps_match()
1447 : Op1(Op1), Op2(Op2), Op3(Op3) {} in ThreeOps_match()
1499 T1 Op2; member
1502 Shuffle_match(const T0 &Op1, const T1 &Op2, const T2 &Mask) in Shuffle_match()
1503 : Op1(Op1), Op2(Op2), Mask(Mask) {} in Shuffle_match()
2130 m_Intrinsic(const T0 &Op0, const T1 &Op1, const T2 &Op2) {
2195 return m_Intrinsic<Intrinsic::fshl>(Op0, Op1, Op2);
[all …]
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86AvoidStoreForwardingBlocks.cpp114 bool alias(const MachineMemOperand &Op1, const MachineMemOperand &Op2) const;
519 const MachineMemOperand &Op2) const { in alias()
520 if (!Op1.getValue() || !Op2.getValue()) in alias()
523 int64_t MinOffset = std::min(Op1.getOffset(), Op2.getOffset()); in alias()
525 int64_t Overlapb = Op2.getSize() + Op2.getOffset() - MinOffset; in alias()
529 MemoryLocation(Op2.getValue(), Overlapb, Op2.getAAInfo())); in alias()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SystemOperands.td749 // Op0 Op1 CRn CRm Op2
754 // Op0 Op1 CRn CRm Op2
761 // Op0 Op1 CRn CRm Op2
1359 // Op0 Op1 CRn CRm Op2
1401 // Op0 Op1 CRn CRm Op2
1406 // Op0 Op1 CRn CRm Op2
1424 // Op0 Op1 CRn CRm Op2
1455 // Op0 Op1 CRn CRm Op2
1471 // Op0 Op1 CRn CRm Op2
1484 // Op0 Op1 CRn CRm Op2
[all …]
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp926 SDValue Op2 = Node->getOperand(2); in ExpandSELECT() local
966 Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2); in ExpandSELECT()
971 Op2 = DAG.getNode(ISD::AND, DL, MaskTy, Op2, NotMask); in ExpandSELECT()
972 SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2); in ExpandSELECT()
1196 SDValue Op2 = Node->getOperand(2); in ExpandVSELECT() local
1229 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2); in ExpandVSELECT()
1234 Op2 = DAG.getNode(ISD::AND, DL, VT, Op2, NotMask); in ExpandVSELECT()
1235 SDValue Val = DAG.getNode(ISD::OR, DL, VT, Op1, Op2); in ExpandVSELECT()
1246 SDValue Op2 = Node->getOperand(2); in ExpandVP_SELECT() local
1266 Op2 = DAG.getNode(ISD::VP_AND, DL, VT, Op2, NotMask, Mask, EVL); in ExpandVP_SELECT()
[all …]

12345