Lines Matching refs:Op2
345 const MachineOperand &Op2 = MI->getOperand(2); in profit() local
347 int32_t Prof2 = Op2.isImm() ? profitImm(Op2.getImm()) : 0; in profit()
727 MachineOperand &Op2 = MI->getOperand(2); in splitCombine() local
744 if (!Op2.isReg()) { in splitCombine()
746 .add(Op2); in splitCombine()
749 .addReg(Op2.getReg(), getRegState(Op2), Op2.getSubReg()); in splitCombine()
779 MachineOperand &Op2 = MI->getOperand(2); in splitShift() local
780 assert(Op0.isReg() && Op1.isReg() && Op2.isImm()); in splitShift()
781 int64_t Sh64 = Op2.getImm(); in splitShift()
903 MachineOperand &Op2 = MI->getOperand(2); in splitAslOr() local
905 assert(Op0.isReg() && Op1.isReg() && Op2.isReg() && Op3.isImm()); in splitAslOr()
919 unsigned RS2 = getRegState(Op2); in splitAslOr()
943 .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR); in splitAslOr()
946 .addReg(Op2.getReg(), RS2, HiSR); in splitAslOr()
950 .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR) in splitAslOr()
954 .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR) in splitAslOr()
963 .addReg(Op2.getReg(), RS2, HiSR) in splitAslOr()
974 .addReg(Op2.getReg(), RS2, LoSR); in splitAslOr()
985 .addReg(Op2.getReg(), RS2, LoSR) in splitAslOr()