142   const MCOperand Op2 = Inst.getOperand(2);  in adjustPqBits()  local
145       ((Op2.isImm() && Op2.getImm() != 0) ||  in adjustPqBits()
146        (Op2.isReg() && Op2.getReg() != Lanai::R0) || (Op2.isExpr())))  in adjustPqBits()
153   if (LPAC::modifiesOp(AluCode) && ((Op2.isImm() && Op2.getImm() != 0) ||  in adjustPqBits()
154                                     (Op2.isReg() && Op2.getReg() != Lanai::R0)))  in adjustPqBits()
190   const MCOperand Op2 = Inst.getOperand(OpNo + 1);  in getRiMemoryOpValue()  local
194   assert((Op2.isImm() || Op2.isExpr()) &&  in getRiMemoryOpValue()
200   if (Op2.isImm()) {  in getRiMemoryOpValue()
201     assert(isInt<16>(Op2.getImm()) &&  in getRiMemoryOpValue()
204     Encoding |= (Op2.getImm() & 0xffff);  in getRiMemoryOpValue()
205     if (Op2.getImm() != 0) {  in getRiMemoryOpValue()
212     getMachineOpValue(Inst, Op2, Fixups, SubtargetInfo);  in getRiMemoryOpValue()
222   const MCOperand Op2 = Inst.getOperand(OpNo + 1);  in getRrMemoryOpValue()  local
227   assert(Op2.isReg() && "Second operand is not register.");  in getRrMemoryOpValue()
228   Encoding |= (getLanaiRegisterNumbering(Op2.getReg()) << 10);  in getRrMemoryOpValue()
261   const MCOperand Op2 = Inst.getOperand(OpNo + 1);  in getSplsOpValue()  local
265   assert((Op2.isImm() || Op2.isExpr()) &&  in getSplsOpValue()
271   if (Op2.isImm()) {  in getSplsOpValue()
272     assert(isInt<10>(Op2.getImm()) &&  in getSplsOpValue()
275     Encoding |= (Op2.getImm() & 0x3ff);  in getSplsOpValue()
276     if (Op2.getImm() != 0) {  in getSplsOpValue()
283     getMachineOpValue(Inst, Op2, Fixups, SubtargetInfo);  in getSplsOpValue()