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Searched refs:Op1Val (Results 1 – 4 of 4) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/
H A DInstCombineNegator.cpp191 const APInt *Op1Val; in visitImpl() local
192 if (match(I->getOperand(1), m_APInt(Op1Val)) && *Op1Val == BitWidth - 1) { in visitImpl()
H A DInstCombineShifts.cpp984 unsigned Op1Val = C->getLimitedValue(BitWidth); in visitShl() local
985 APInt Bits = APInt::getHighBitsSet(BitWidth, BitWidth - Op1Val); in visitShl()
1139 unsigned Op1Val = C->getLimitedValue(BitWidth); in visitLShr() local
1140 APInt Bits = APInt::getLowBitsSet(BitWidth, BitWidth - Op1Val); in visitLShr()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64InstPrinter.cpp783 unsigned Op1Val = Op1.getImm(); in printSysAlias() local
791 Encoding |= Op1Val << 11; in printSysAlias()
802 switch (Op1Val) { in printSysAlias()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp24880 const APInt &Op1Val = Op1C->getAPIntValue(); in LowerSETCC() local
24881 if (!Op1Val.isZero()) { in LowerSETCC()
24883 if ((CC == ISD::CondCode::SETGT && !Op1Val.isMaxSignedValue()) || in LowerSETCC()
24884 (CC == ISD::CondCode::SETUGT && !Op1Val.isMaxValue())) { in LowerSETCC()
24885 APInt Op1ValPlusOne = Op1Val + 1; in LowerSETCC()
24887 (!Op1Val.isSignedIntN(8) || Op1ValPlusOne.isSignedIntN(8))) { in LowerSETCC()