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Searched refs:Offset0 (Results 1 – 17 of 17) sorted by relevance

/llvm-project-15.0.7/llvm/unittests/CodeGen/
H A DSelectionDAGAddressAnalysisTest.cpp160 TypeSize Offset0 = TypeSize::Fixed(0); in TEST_F() local
162 SDValue Index0 = DAG->getMemBasePlusOffset(FIPtr, Offset0, Loc); in TEST_F()
165 PtrInfo.getWithOffset(Offset0)); in TEST_F()
285 TypeSize Offset0 = TypeSize::Fixed(0); in TEST_F() local
287 SDValue Index0 = DAG->getMemBasePlusOffset(FIPtr, Offset0, Loc); in TEST_F()
290 PtrInfo.getWithOffset(Offset0)); in TEST_F()
326 TypeSize Offset0 = TypeSize::Fixed(0); in TEST_F() local
328 SDValue Index0 = DAG->getMemBasePlusOffset(FIPtr, Offset0, Loc); in TEST_F()
331 PtrInfo.getWithOffset(Offset0)); in TEST_F()
361 TypeSize Offset0 = TypeSize::Fixed(0); in TEST_F() local
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/llvm-project-15.0.7/llvm/unittests/DebugInfo/DWARF/
H A DDWARFListTableTest.cpp94 Optional<uint64_t> Offset0 = Header.getOffsetEntry(Extractor, 0); in TEST() local
95 EXPECT_TRUE(!!Offset0); in TEST()
96 EXPECT_EQ(Offset0, uint64_t(4)); in TEST()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMHazardRecognizer.cpp192 int64_t Offset0 = 0; in getHazardType() local
210 Ptr0 = GetPointerBaseWithConstantOffset(BaseVal0, Offset0, DL, true); in getHazardType()
213 return CheckOffsets(Offset0, Offset1); in getHazardType()
222 Offset0 = MF.getFrameInfo().getObjectOffset(FS0->getFrameIndex()); in getHazardType()
224 return CheckOffsets(Offset0, Offset1); in getHazardType()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.h156 bool isDSOffset2Legal(SDValue Base, unsigned Offset0, unsigned Offset1,
159 bool SelectDS64Bit4ByteAligned(SDValue Ptr, SDValue &Base, SDValue &Offset0,
161 bool SelectDS128Bit8ByteAligned(SDValue Ptr, SDValue &Base, SDValue &Offset0,
163 bool SelectDSReadWrite2(SDValue Ptr, SDValue &Base, SDValue &Offset0,
H A DAMDGPUISelDAGToDAG.cpp1139 bool AMDGPUDAGToDAGISel::isDSOffset2Legal(SDValue Base, unsigned Offset0, in isDSOffset2Legal() argument
1142 if (Offset0 % Size != 0 || Offset1 % Size != 0) in isDSOffset2Legal()
1144 if (!isUInt<8>(Offset0 / Size) || !isUInt<8>(Offset1 / Size)) in isDSOffset2Legal()
1158 SDValue &Offset0, in SelectDS64Bit4ByteAligned() argument
1160 return SelectDSReadWrite2(Addr, Base, Offset0, Offset1, 4); in SelectDS64Bit4ByteAligned()
1164 SDValue &Offset0, in SelectDS128Bit8ByteAligned() argument
1166 return SelectDSReadWrite2(Addr, Base, Offset0, Offset1, 8); in SelectDS128Bit8ByteAligned()
1170 SDValue &Offset0, SDValue &Offset1, in SelectDSReadWrite2() argument
1184 Offset0 = CurDAG->getTargetConstant(OffsetValue0 / Size, DL, MVT::i8); in SelectDSReadWrite2()
1235 Offset0 = CurDAG->getTargetConstant(OffsetValue0 / Size, DL, MVT::i8); in SelectDSReadWrite2()
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H A DAMDGPUInstructionSelector.h238 bool isDSOffset2Legal(Register Base, int64_t Offset0, int64_t Offset1,
H A DSIInstrInfo.cpp176 int64_t &Offset0, in areLoadsFromSameBasePtr() argument
244 Offset0 = Load0Offset->getZExtValue(); in areLoadsFromSameBasePtr()
277 Offset0 = cast<ConstantSDNode>(Off0)->getZExtValue(); in areLoadsFromSameBasePtr()
335 unsigned Offset0 = Offset0Op->getImm(); in getMemOperandsWithOffsetWidth() local
337 if (Offset0 + 1 != Offset1) in getMemOperandsWithOffsetWidth()
356 Offset = EltSize * Offset0; in getMemOperandsWithOffsetWidth()
528 int64_t Offset0, int64_t Offset1, in shouldScheduleLoadsNear() argument
530 assert(Offset1 > Offset0 && in shouldScheduleLoadsNear()
536 return (NumLoads <= 16 && (Offset1 - Offset0) < 64); in shouldScheduleLoadsNear()
3140 int64_t Offset0, Offset1; in checkInstOffsetsDoNotOverlap() local
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H A DAMDGPUInstructionSelector.cpp1346 unsigned Offset0 = OrderedCountIndex << 2; in selectDSOrderedIntrinsic() local
1355 unsigned Offset = Offset0 | (Offset1 << 8); in selectDSOrderedIntrinsic()
4342 bool AMDGPUInstructionSelector::isDSOffset2Legal(Register Base, int64_t Offset0, in isDSOffset2Legal() argument
4345 if (Offset0 % Size != 0 || Offset1 % Size != 0) in isDSOffset2Legal()
4347 if (!isUInt<8>(Offset0 / Size) || !isUInt<8>(Offset1 / Size)) in isDSOffset2Legal()
H A DSIInstrInfo.h205 bool shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, int64_t Offset0,
H A DSIInstrInfo.td1222 def offset0 : NamedOperandU8<"Offset0", NamedMatchClass<"Offset0">>;
H A DSIISelLowering.cpp7239 unsigned Offset0 = OrderedCountIndex << 2; in LowerINTRINSIC_W_CHAIN() local
7248 unsigned Offset = Offset0 | (Offset1 << 8); in LowerINTRINSIC_W_CHAIN()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp410 int64_t Offset0; in apply() local
412 MachineOperand *BaseOp0 = HII.getBaseAndOffset(L0, Offset0, Size0); in apply()
431 if (((Offset0 ^ Offset1) & 0x18) != 0) in apply()
H A DHexagonISelLoweringHVX.cpp1985 SDValue Offset0 = DAG.getTargetConstant(0, dl, ty(Base)); in LowerHvxMaskedOp() local
1989 {Mask, Base, Offset0, Value, Chain}, DAG); in LowerHvxMaskedOp()
2016 {MaskU.first, Base, Offset0, ValueU.first, Chain}, DAG); in LowerHvxMaskedOp()
/llvm-project-15.0.7/llvm/test/CodeGen/SPARC/
H A D64abi.ll475 ; HARD-DAG: std %f4, [%sp+[[Offset0:[0-9]+]]]
477 ; HARD-DAG: ldx [%sp+[[Offset0]]], %o2
490 ; HARD: st %f1, [%fp+[[Offset0:[0-9]+]]]
495 ; HARD: ld [%fp+[[Offset0]]], %f1
/llvm-project-15.0.7/llvm/lib/Analysis/
H A DConstantFolding.cpp1305 APInt Offset0(IndexWidth, 0); in ConstantFoldCompareInstOperands() local
1307 Ops0->stripAndAccumulateInBoundsConstantOffsets(DL, Offset0); in ConstantFoldCompareInstOperands()
1314 ConstantInt::get(CE0->getContext(), Offset0), in ConstantFoldCompareInstOperands()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp16401 const APInt &Offset0 = CN->getAPIntValue(); in CombineToPreIndexedLoadStore() local
16410 APInt CNV = Offset0; in CombineToPreIndexedLoadStore()
18574 int64_t Offset0 = LoadNodes[0].OffsetFromBase; in tryStoreMergeOfLoads() local
18577 if (Offset0 - Offset1 == ElementSizeBytes && in tryStoreMergeOfLoads()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp8444 bool Offset0 = false, Offset1 = false; in getFauxShuffleMask() local
8456 Offset0 = true; in getFauxShuffleMask()
8481 if (Offset0 || Offset1) { in getFauxShuffleMask()
8483 if ((Offset0 && isInRange(M, 0, NumElts)) || in getFauxShuffleMask()